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| ksz8895mq/rq/fmq integrated 5 - port 10/100 managed ethernet switch with mii/rmii i nterface rev. 1. 6 micrel inc. ? 2180 fortune dr ive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com january 22, 2013 revision 1. 6 general description the ksz8895mq/rq/fmq is a highly - integrated , layer 2 managed , five - port switch with numerous features designed to reduce system cost . intend ed for cost - sensitive 10/100mbps five - port switch systems with low power consumption, on - chip t ermination , and internal core power controller s , i t supports hi gh - performance memory bandwidth and shared memory - based switch fabric with non - blocking configuration. it s e xtensive feature set i ncludes power management, programmable rate limit and priority ratio , tag/port - based vlan, packets filtering, four - queue qos priorit ization , management interfaces , and mib counters. the ksz8895 family provides multiple cpu data interfaces to effectively address both current and emerging fast ethernet applications wh en port 5 is configured to separate mac5 with sw5 - mii/ rmii and phy5 with p5 - mii/rmii interfaces. the ksz88 95 family offers three configurations, p roviding the flexibility to meet different requirements : ? ksz88 95 m q : five 10/100b ase - t/tx transceiver s , one sw5 - mii and one p5 - mii interface ? ksz88 95rq : five 10/100b ase - t/tx transceivers , one sw5 - r mii and one p5 - rmii interface ? ksz88 95fmq : three 10/100b ase - t/tx transceiv er s on ports 1, 2, 5 and two 100base - fx transceivers on ports 3, 4, one sw5 - mii and one p5 - mii interface all registers of macs and phy s units can be managed by the spi or the smi interface . miim registers can be accessed through the mdc/mdio interface . eeprom can set all control registers for the unmanaged mode. functional diagram not e : sw5 in dicate s the mac5 of the switch side, p5 indicate s the phy5 of the port 5 .
micrel, inc. ksz8895mq/rq/fmq january 22, 2013 2 r evision 1. 6 features advanced switch features ? ieee 802.1q vlan support for up to 128 active vlan groups (full - range 4096 of vlan ids) . ? static mac table supports up to 32 entries. ? vlan id tag/un tag options, per port basis ? ieee 802.1p/q tag insertion or removal on a per port basis based on ingress port (egress) . ? programmable rate limiting at the ingress and egress on a per port basis . ? jitter - free per packet based rate limiting support . ? broadcast s torm protection with percentage control (global and per port basis) . ? ieee 802.1d rapid spanning tree protocol rstp support . ? tail tag mode (1 byte added before fcs) support at port 5 to inform the processor which ingress port receives the packet . ? 1.4 gbps hi gh- performance memory bandwidth and shared memory - based switch fabric with fully non- blocking configuration . ? dual mii with mac5 and phy5 on port 5, sw 5 - mii/rmii for mac 5 and p5 - mii/rmii for phy 5. ? e nable/disable option for huge frame size up to 2000 byte s per frame . ? igmp v1/v2 snooping (ipv4 ) support for multicast packet f iltering . ? ipv4/ipv6 qo s support . ? support unknow n unicast/multicast address and unknown vid packet filtering . ? self - address filtering. comprehensive configuration register access ? serial ma nagement interface (mdc/mdio) to all phy s registers and smi interface (mdc/mdio) to all registers . ? high speed spi (up to 25mhz) and i 2 c master interface to all internal registers . ? i/0 pins strapping and eeprom to program selective registers in unmanaged sw itch mode . ? control registers configurable on the fly (port - priority, 802.1p/d/q, an ). qos/cos packet prioritization support ? p er port, 802.1p and diffserv - based . ? 1/2/4 - queue qos prioritization selection. ? programmable weighted fair queuing for ratio control . ? r e - mapping of 802.1p priority field per port basis . integrated five - port 10/100 ethernet switch ? new generation switch with five macs and five phys with fully compliant with ieee 802.3u standard . ? phys designed with patented enhanced mixed - signal technolog y . ? non - blocking switch fabric assures fast packet delivery by utilizing a 1k mac address lookup table and a store - and - forward architecture . ? on - chip 64kbyte memory for frame buffering ( not shared with 1k unicast address table) . ? full duplex ieee 802.3x flow control (pause) with force mode option . ? half - duplex back pressure flow control . ? hp auto mdi/mdi - x and ieee auto crossover support . ? sw - mii interface supports both mac mode and phy mode . ? 7 - wire serial network interface (sni) support for legacy mac . ? per port led indicators for link, activity, and 10/100 speed . ? register port status support for link, activity, full/half duplex and 10/100 speed . ? o n - chip terminations and internal biasing technology for cost down and lowest power consumption. switch monitoring fea tures ? port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or mii . ? mib counters for fully compliant statistics gathering 34 mib counters per port . ? loop- back support for mac, phy and remote diagnostic of failure . ? interrupt for the l ink change on any ports. low power dissipation ? full - chip hardware power - down. ? full - chip software power - down and per port software power down . ? energy - detect mode support < 100m w full chip - power consumption when all ports have no activity . ? very low full chip power consumption (<0.5w) , without extra power consumption on transformers . ? dynamic clock tree shutdown feature . ? voltages: single 3.3v supply with 3.3v vddio and internal 1.2v ldo controller enabled , or external 1.2v ldo solution . ? analog vddat 3. 3v only . ? vddio support 3. 3v, 2.5v and 1.8v . ? low 1.2v core power . ? 0. 13 m cmos technology . ? c ommercial temperature range: 0 c to +70c . ? i ndustrial temperature range : -40 c to +85c . ? available in 128- p in p qfp, l ead - free package . m icrel, inc. confidential ksz8895mq/rq/fmq january 22, 2013 3 r evision 1. 6 applications ? typical ? voip p hone ? set - top /game b ox ? automotive ? industrial c ontrol ? iptv pof ? soho residential g ateway ? broadband gateway/f irewall/ vpn ? integrated dsl/cable m odem ? wireless lan access point + gateway ? standalone 10/100 switch ordering information part number temperature range p ackage lead finish/grade ksz8895mq 0 c to 70c 128- pin p qfp pb - free/commercial ksz8895mqi -40 c to +85c 128- pin p qfp pb - free/industrial ksz8895 r q 0 c to 70c 128- pin p qfp pb - free/commercial ksz8895 r qi -40 c to +85c 128- pin p qfp pb - free/industrial ks z8895f mq 0 c to 70c 128- pin p qfp pb - free/commercial ksz8895 f mqi -40 c to +85c 128- pin p qfp pb - free/industrial revision history revision date description 1.0 09/13/10 initial document created 1. 1 11/1 6 /10 remove tmq part 1. 2 01/ 20 /1 1 update the ord ering information and some data. 1. 3 03/18/11 update the register number, descriptions and correct typo error. 1. 4 08/30/11 correct typo error for package information and update some descriptions for smi mode and igmp and update register default values , pins type and some parameters. 1. 5 02/ 2 4/12 update descriptions for pin, register 1 chip id , port register, vlan table and i2c master . update the equation in the broadcast storm protection section. update table of strap - in pins. update the ordering inf ormation for rq parts. 1. 6 11/ 28/ 1 2 update the ordering information for fm q parts available . correct typo s. up date the operation rating to 5% and ttl min/max i/o voltage in different vddio. add register 165 for fmq part with fiber mode. update a note fo r pin 125 descriptions . micrel, inc. ksz8895mq/rq/fmq january 22, 2013 4 r evision 1. 6 contents pin configuration .......................................................................................................................................................... 13 pin description .............................................................................................................................................................. 14 pin for strap - in options ................................................................................................................................................ 21 introduction ................................................................................................................................................................... 24 functional overview: phy sical layer transceiver .................................................................................................... 24 100base - tx transmit ............................................................................................................................................... 24 100base - tx receive ................................................................................................................................................ 24 pll clock synthesizer ................................................................................................................................................ 25 scrambler/descrambler (100base - tx only) ............................................................................................................. 25 100base - fx operation .............................................................................................................................................. 25 100base - fx signal detection ................................................................................................................................... 25 100base - fx far end fault ........................................................................................................................................ 25 10base - t transmit .................................................................................................................................................... 25 10base - t receive ..................................................................................................................................................... 25 mdi/mdi - x auto crossover ........................................................................................................................................ 25 straight cable ......................................................................................................................................................... 26 crossover cable ..................................................................................................................................................... 27 auto - negotiation ......................................................................................................................................................... 27 on - chip termination resistors ................................................................................................................................... 29 internal 1.2v ldo controller ...................................................................................................................................... 29 functional overview: power management ................................................................................................................. 29 normal operation mode ............................................................................................................................................. 29 energy detect mode ................................................................................................................................................... 30 soft power down mode .............................................................................................................................................. 30 power saving mode .................................................................................................................................................... 30 port - based power down mode ................................................................................................................................... 30 functional overview: switch core .............................................................................................................................. 30 address look - up ........................................................................................................................................................ 30 learning ...................................................................................................................................................................... 30 migration ..................................................................................................................................................................... 31 aging ........................................................................................................................................................................... 31 forwarding .................................................................................................................................................................. 31 switching engine ........................................................................................................................................................ 31 medi a access controller (mac) operation ................................................................................................................ 31 inter - packet gap (ipg) ........................................................................................................................................... 31 backoff algorithm .................................................................................................................................................... 31 late collision .......................................................................................................................................................... 31 illegal frames ......................................................................................................................................................... 32 flow control ............................................................................................................................................................ 32 half - duplex back pressure .................................................................................................................................... 35 broadcast storm protection .................................................................................................................................... 35 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 5 r evision 1. 6 mii interface operation ............................................................................................................................................... 36 port 5 phy 5 p5 - mii/rmii interface ............................................................................................................................ 36 port 5 mac 5 sw5 - mii interface for the ksz8895mq/fmq ...................................................................................... 37 p ort 5 mac 5 switch sw5 - rmii interface for the ksz8895rq ................................................................................. 38 sni interface operation .............................................................................................................................................. 40 advanced functionality ................................................................................................................................................ 41 qos priority support ................................................................................................................................................... 41 port - based priority .................................................................................................................................................. 41 802.1p - based priority ............................................................................................................................................. 41 diffserv - based priority ........................................................................................................................................... 42 spanning tree support ............................................................................................................................................... 42 rapid spanning tree support .................................................................................................................................... 43 tail tagging mode ...................................................................................................................................................... 44 igmp support ............................................................................................................................................................. 45 port mirroring s upport ................................................................................................................................................ 45 vlan support ............................................................................................................................................................. 45 rate limiting support ................................................................................................................................................. 46 ingress rate limit ................................................................................................................................................... 46 egress rate limit ................................................................................................................................................... 47 transmit queue ratio programming ...................................................................................................................... 47 filtering for self - address, unknown unicast/ m ulticast a ddress and u nknown vid p acket/ip m ulticast .................. 47 configuration interface ............................................................................................................................................... 47 i 2 c master serial bus configuration ....................................................................................................................... 47 spi slave serial bus configuration ........................................................................................................................ 48 mii management interface (miim) .......................................................................................................................... 51 serial management interface (smi) ........................................................................................................................ 51 register description ..................................................................................................................................................... 53 global registers ......................................................................................................................................................... 55 register 0 (0x00): chip id0 .................................................................................................................................... 55 register 1 (0x01): chip id1 / start switch .............................................................................................................. 55 register 2 (0x02): global control 0 ........................................................................................................................ 55 register 3 (0x03): global control 1 ........................................................................................................................ 56 register 4 (0x04): global control 2 ........................................................................................................................ 57 register 5 (0x05): global control 3 ........................................................................................................................ 58 register 6 (0x07): global control 4 ........................................................................................................................ 59 register 7 (0x07): global control 5 ........................................................................................................................ 60 register 8 (0x08): global control 6 ........................................................................................................................ 60 register 9 (0x09): global contr ol 7 ........................................................................................................................ 60 register 10 (0x0a): global control 8 ...................................................................................................................... 61 register 11 (0x0b): global control 9 ...................................................................................................................... 61 register 12 (0x0c): global control 10 ................................................................................................................... 62 register 13 (0x0d): global control 11 ................................................................................................................... 62 register 14 (0x0e): po wer down management control 1 ..................................................................................... 62 register 15 (0x0f): power down management control 2 ...................................................................................... 63 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 6 r evision 1. 6 port registers ............................................................................................................................................................. 64 register 16 (0x10): port 1 control 0 ....................................................................................................................... 64 register 32 (0x20): port 2 control 0 ....................................................................................................................... 64 regist er 48 (0x30): port 3 control 0 ....................................................................................................................... 64 register 64 (0x40): port 4 control 0 ....................................................................................................................... 64 register 80 (0x50): port 5 control 0 ....................................................................................................................... 64 register 17 (0x11): port 1 control 1 ....................................................................................................................... 65 register 33 (0x21): port 2 control 1 ....................................................................................................................... 65 register 49 (0x31): port 3 control 1 ....................................................................................................................... 65 register 65 (0x41): port 4 control 1 ....................................................................................................................... 65 register 81 (0x51): port 5 control 1 ....................................................................................................................... 65 register 18 (0x12): port 1 control 2 ....................................................................................................................... 66 register 34 (0x22): port 2 control 2 ....................................................................................................................... 66 register 50 (0x32): port 3 control 2 ....................................................................................................................... 66 register 66 (0x42): port 4 control 2 ....................................................................................................................... 66 register 82 (0x52): port 5 control 2 ....................................................................................................................... 66 register 19 (0x13): port 1 control 3 ....................................................................................................................... 67 register 35 (0x23): port 2 control 3 ....................................................................................................................... 67 register 51 (0x33): port 3 control 3 ....................................................................................................................... 67 register 67 (0x43): port 4 control 3 ....................................................................................................................... 67 register 83 (0x53): port 5 con trol 3 ....................................................................................................................... 67 register 20 (0x14): port 1 control 4 ....................................................................................................................... 67 register 36 (0x24): port 2 control 4 ....................................................................................................................... 67 register 52 (0x34): port 3 control 4 ....................................................................................................................... 67 register 68 (0x44): port 4 control 4 ....................................................................................................................... 67 register 84 (0x54): po rt 5 control 4 ....................................................................................................................... 67 register 87 (0x57): rmii management control register ....................................................................................... 67 register 25 (0x19): port 1 status 0 ........................................................................................................................ 68 register 41 (0x29): port 2 status 0 ........................................................................................................................ 68 register 57 (0x39): port 3 status 0 ........................................................................................................................ 68 r egister 73 (0x49): port 4 status 0 ........................................................................................................................ 68 register 89 (0x59): port 5 status 0 ........................................................................................................................ 68 register 26 (0x1a): port 1 phy special control/stat us ......................................................................................... 68 register 42 (0x2a): port 2 phy special control/status ......................................................................................... 68 register 58 (0x3a): port 3 phy special control/status ......................................................................................... 68 register 74 (0x4a): port 4 phy special control/status ......................................................................................... 68 register 90 (0x5a): port 5 phy special control/status ......................................................................................... 68 register 27 (0x1b): reserved ................................................................................................................................ 69 register 43 (0x2b): reserved ................................................................................................................................ 69 register 59 (0x3b): re served ................................................................................................................................ 69 register 75 (0x4b): reserved ................................................................................................................................ 69 register 91 (0x5b): reserved ................................................................................................................................ 69 register 28 (0x1c): port 1 control 5 ...................................................................................................................... 69 register 44 (0x2c): port 2 control 5 ...................................................................................................................... 69 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 7 r evision 1. 6 register 60 (0x3c): port 3 control 5 ...................................................................................................................... 69 register 76 (0x4c): port 4 control 5 ...................................................................................................................... 69 register 92 (0x5c): port 5 control 5 ...................................................................................................................... 69 register 29 (0x1d): port 1 control 6 ...................................................................................................................... 70 register 45 (0x2d): port 2 control 6 ...................................................................................................................... 70 register 61 (0x3d): port 3 con trol 6 ...................................................................................................................... 70 register 77 (0x4d): port 4 control 6 ...................................................................................................................... 70 register 93 (0x5d): port 5 control 6 ...................................................................................................................... 70 register 30 (0x1e): port 1 status 1 ........................................................................................................................ 71 register 46 (0x2e): port 2 status 1 ........................................................................................................................ 71 register 62 (0x3e): port 3 status 1 ........................................................................................................................ 71 register 78 (0x4e): port 4 status 1 ........................................................................................................................ 71 register 94 (0x5e): port 5 status 1 ........................................................................................................................ 71 register 31 (0x1f): port 1 control 7 and status 2 ................................................................................................. 71 register 47 (0x2f): port 2 control 7 and status 2 ................................................................................................. 71 register 63 (0x3f): port 3 control 7 and status 2 ................................................................................................. 71 register 79 (0x4f): port 4 control 7 and status 2 ................................................................................................. 71 register 95 (0x 5f): port 5 control 7 and status 2 ................................................................................................. 71 advanced control registers ....................................................................................................................................... 72 register 104 (0x68): mac address register 0 ...................................................................................................... 72 register 105 (0x69): mac address register 1 ...................................................................................................... 72 register 106 (0x6a): mac address register 2 ...................................................................................................... 72 register 107 (0x6b): mac address register 3 ...................................................................................................... 72 register 108 (0x6c): mac address register 4 ...................................................................................................... 72 register 109 (0x6 d): mac address register 5 ..................................................................................................... 72 register 110 (0x6e): indirect access control 0 ..................................................................................................... 73 register 111 (0x6f): indirect access control 1 ...................................................................................................... 73 register 112 (0x70): indirect data register 8 ........................................................................................................ 74 register 113 (0x71): indirect data register 7 ........................................................................................................ 74 register 114 (0x72): indirect data register 6 ........................................................................................................ 74 register 115 (0x73): indirect data register 5 ........................................................................................................ 74 register 116 (0x74): indirect data register 4 ........................................................................................................ 74 register 117 (0x75): indirect data register 3 ........................................................................................................ 74 register 118 (0x76): ind irect data register 2 ........................................................................................................ 74 register 119 (0x77): indirect data register 1 ........................................................................................................ 74 register 120 (0x78): indirect data register 0 ........................................................................................................ 74 register 124 (0x7c): interrupt status register ...................................................................................................... 74 register 125 (0x7d): interrupt mask register ........................................................................................................ 75 register 128 (0x80): global control 12 .................................................................................................................. 75 register 129 (0x81): global control 13 .................................................................................................................. 75 register 130 (0 x82): global control 14 .................................................................................................................. 76 register 131 (0x83): global control 15 .................................................................................................................. 76 register 132 (0x84): global control 16 .................................................................................................................. 77 register 133(0x85): global control 17 ................................................................................................................... 77 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 8 r evision 1. 6 register 134 (0x86): global control 18 .................................................................................................................. 77 register 135 (0x87): global control 19 .................................................................................................................. 78 register 144 (0x90): tos priority control register 0 ............................................................................................ 78 register 145 (0x91): tos pri ority control register 1 ............................................................................................ 79 register 146 (0x92): tos priority control register 2 ............................................................................................ 79 register 147 (0x93): tos priority control re gister 3 ............................................................................................ 79 register 148 (0x94): tos priority control register 4 ............................................................................................ 79 register 149 (0x95): tos priority control register 5 ............................................................................................ 80 register 150 (0x96): tos priority control register 6 ............................................................................................ 80 register 151 (0x97): tos priority control register 7 ............................................................................................ 80 register 152 (0x98): tos priority control register 8 ............................................................................................ 80 register 153 (0x99): tos priority control register 9 ............................................................................................ 80 register 154 (0x9a): tos priority control register 10 .......................................................................................... 80 register 155 (0x9b): tos priority control register 11 .......................................................................................... 80 register 156 (0x9c): tos priority control register 12 .......................................................................................... 81 register 157 (0x9d): tos priority control register 13 .......................................................................................... 81 register 158 (0x9e): tos priority control register 14 .......................................................................................... 81 register 159 (0x9f): tos priority control register 15 .......................................................................................... 81 register 1 65 ( 0 xa5 ): fiber control register .......................................................................................................... 81 register 176 (0xb0): port 1 control 8 .................................................................................................................... 82 register 192 (0xc0): port 2 control 8 .................................................................................................................... 82 register 208 (0xd0): port 3 control 8 .................................................................................................................... 82 register 224 (0xe0): port 4 control 8 .................................................................................................................... 82 register 240 (0xf0): port 5 control 8 ..................................................................................................................... 82 register 177 (0xb1): port 1 control 9 .................................................................................................................... 83 register 193 (0xc1): port 2 control 9 .................................................................................................................... 83 register 209 (0xd1): port 3 control 9 .................................................................................................................... 83 register 225 (0xe1): port 4 control 9 .................................................................................................................... 83 register 241 (0xf1): port 5 control 9 ..................................................................................................................... 83 register 178 (0xb2): port 1 control 10 .................................................................................................................. 84 register 194 (0xc2): port 2 control 10 .................................................................................................................. 84 register 210 (0xd2): port 3 control 10 .................................................................................................................. 84 register 226 (0xe2): port 4 control 10 .................................................................................................................. 84 register 242 (0xf2): port 5 control 10 ................................................................................................................... 84 register 179 (0xb3): port 1 control 11 .................................................................................................................. 84 register 195 (0xc3): port 2 control 11 .................................................................................................................. 84 register 211 (0xd3): port 3 control 11 .................................................................................................................. 84 register 227 (0xe3): port 4 control 11 .................................................................................................................. 84 register 243 (0xf3): port 5 control 11 ................................................................................................................... 84 register 180 (0xb4): port 1 control 12 .................................................................................................................. 84 register 196 (0xc4): port 2 control 12 .................................................................................................................. 84 register 212 (0xd4): port 3 control 12 .................................................................................................................. 84 register 228 (0xe4): port 4 control 12 .................................................................................................................. 84 register 244 (0xf4): port 5 control 12 ................................................................................................................... 84 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 9 r evision 1. 6 register 181 (0xb5): port 1 control 13 .................................................................................................................. 85 register 197 (0xc5): port 2 control 13 .................................................................................................................. 85 register 213 (0xd5): port 3 control 13 .................................................................................................................. 85 register 229 (0xe 5): port 4 control 13 .................................................................................................................. 85 register 245 (0xf5): port 5 control 13................................................................................................................... 85 register 182 (0xb6): port 1 rate limit control ...................................................................................................... 85 register 198 (0xc6): port 2 rate limit control ...................................................................................................... 85 register 214 (0xd6): port 3 rate limit control ...................................................................................................... 85 register 230 (0xe6): port 4 rate limit control ...................................................................................................... 85 register 246 (0xf6): port 5 rate limit control ...................................................................................................... 85 reg ister 183 (0xb7): port 1 priority 0 ingress limit control 1 ................................................................................ 86 register 199 (0xc7): port 2 priority 0 ingress limit control 1 ............................................................................... 86 register 215 (0xd7): port 3 priority 0 ingress limit control 1 ............................................................................... 86 register 231 (0xe7): port 4 priority 0 ingress limit control 1 ................................................................................ 86 register 247 (0xf7): port 5 priority 0 ingress limit control 1 ................................................................................ 86 register 184 (0xb8): port 1 priority 1 ingress limit control 2 ................................................................................ 86 register 200 (0xc8): port 2 priority 1 ingress limit control 2 ............................................................................... 86 register 216 (0xd8): port 3 priority 1 ingress limit control 2 ............................................................................... 86 register 232 (0xe8): port 4 priority 1 ingress limit control 2 ................................................................................ 86 register 248 (0xf8): port 5 priority 1 ingress limit control 2 ................................................................................ 86 register 185 (0xb9): port 1 priority 2 ingress limit control 3 ................................................................................ 86 register 201 (0xc9): port 2 priority 2 ingress limit control 3 ............................................................................... 86 register 217 (0xd9): port 3 priority 2 ingress limit control 3 ............................................................................... 86 register 233 (0xe9): port 4 priority 2 ingress limit control 3 ................................................................................ 86 register 249 (0xf9): port 5 priority 2 ingress limit control 3 ................................................................................ 86 register 186 (0xba): port 1 priority 3 ingress limit control 4 ............................................................................... 86 register 202 (0xca): port 2 priority 3 ingress limit control 4 ............................................................................... 86 register 218 (0xda): port 3 priority 3 ingress limit control 4 ............................................................................... 86 register 234 (0xea): port 4 priority 3 ingress limit control 4 ............................................................................... 86 register 250 (0xfa): port 5 priority 3 ingress limit control 4 ............................................................................... 86 register 187 (0xbb): port 1 queue 0 egress limit control 1 ................................................................................ 87 register 203 (0xcb): port 2 queue 0 egress limit control 1 ................................................................................ 87 register 219 (0xdb): port 3 queue 0 egress limit control 1 ................................................................................ 87 register 235 (0xeb): port 4 queue 0 egress limit control 1 ................................................................................ 87 register 251 (0xfb): port 5 queue 0 egress limit control 1 ................................................................................ 87 register 188 (0xbc) : port 1 queue 1 egress limit control 2 ............................................................................... 87 register 204 (0xcc) : port 2 queue 1 egress limit control 2 ............................................................................... 87 register 220 (0xdc) : port 3 queue 1 egress limit control 2 ............................................................................... 87 register 236 (0xec) : port 4 queue 1 egress limit control 2 ............................................................................... 87 register 252 (0xfc) : port 5 queue 1 egress limit control 2 ............................................................................... 87 register 189 (0xbd): port 1 queue 2 egress limit control 3 ................................................................................ 87 register 205 (0xcd): port 2 queue 2 egress limit control 3 ................................................................................ 87 register 221 (0xdd): port 3 queue 2 egress limit control 3 ................................................................................ 87 register 237 (0xed): port 4 queue 2 egress limit control 3 ................................................................................ 87 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 10 r evision 1. 6 register 253 (0xfd): port 5 queue 2 egress limit control 3 ................................................................................ 87 register 190 (0xbe) : port 1 queue 3 egress limit control 4 ............................................................................... 88 register 206 (0xce) : port 2 queue 3 egress limit control 4 ............................................................................... 88 register 222 (0xde) : port 3 queue 3 egress limit control 4 ............................................................................... 88 register 238 (0xee): port 4 queue 3 egress limit control 4 ................................................................................ 88 register 254 (0xfe): port 5 queue 3 egress limit control 4 ................................................................................ 88 data rate selection table in 100bt .......................................................................................................................... 89 data rate selection table in 10bt ............................................................................................................................ 89 register 191(0xbf): testing register .................................................................................................................... 90 register 207(0xcf): reserved control register ................................................................................................... 90 register 223(0xdf): test register 2 ...................................................................................................................... 90 register 239(0xef): test register 3 ...................................................................................................................... 90 register 255(0xff): testing register 4 .................................................................................................................. 90 static mac address table ........................................................................................................................................... 91 vlan table .................................................................................................................................................................... 93 dynamic mac address table ...................................................................................................................................... 95 mib (management informat ion base) counters ......................................................................................................... 96 miim registers ............................................................................................................................................................... 99 register 0h: mii control .............................................................................................................................................. 99 register 1h: mii status ............................................................................................................................................. 100 register 2h: phyid high ........................................................................................................................................ 100 register 3h: phyid low ......................................................................................................................................... 100 register 4h: advertisement ability ............................................................................................................................ 100 register 5h: link partner ability ............................................................................................................................... 101 register 1dh: reserved ........................................................................................................................................... 101 register 1fh: phy special control/status ................................................................................................................ 101 absolute maximum ratings (1) .................................................................................................................................... 103 operating ratings (2) .................................................................................................................................................... 103 electrical characteristics (4, 5) ...................................................................................................................................... 103 timing diagrams ......................................................................................................................................................... 105 eeprom timing ....................................................................................................................................................... 105 sni timing ................................................................................................................................................................ 106 mii timing ................................................................................................................................................................. 107 rmii timing ............................................................................................................................................................... 109 spi timing ................................................................................................................................................................ 110 auto - negotiation timing ........................................................................................................................................... 112 mdc/mdio timing .................................................................................................................................................... 113 reset timing ............................................................................................................................................................. 114 reset circuit diagram ............................................................................................................................................... 115 selection of isolation transformer (1) ......................................................................................................................... 116 selection of reference crystal .................................................................................................................................. 116 package information ................................................................................................................................................... 117 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 11 r evision 1. 6 list of figures figure 1. typical straight cable connection ............................................................................................................... 26 figure 2. typical crossover cable connection ........................................................................................................... 27 figure 3. auto - negotiation ........................................................................................................................................... 28 figure 4. destination address lookup flow chart, stage 1 ........................................................................................ 33 figure 5. destination address resolution flow chart, stage 2 ................................................................................... 34 figure 6. 802.1p priority field format .......................................................................................................................... 41 figure 7 . tail tag frame format .................................................................................................................................. 44 figure 8 . ksz8895mq/rq/fmq eeprom c onfiguration timing diagram ................................................................ 48 figure 9 . spi write data cycle .................................................................................................................................... 49 figure 10 . s pi read data cycle .................................................................................................................................. 49 figure 11 . spi multiple write ....................................................................................................................................... 50 figure 12 . spi multiple read ....................................................................................................................................... 50 figure 13 . eeprom interface input receive timing diagram .................................................................................. 105 figure 14 . eeprom interface output transmit timing diagram .............................................................................. 105 figure 15 . sni input timing ....................................................................................................................................... 106 figure 16 . sni output timing .................................................................................................................................... 106 figure 17. mac mode mii timing ? data received from mii .................................................................................... 107 figure 18. mac mode mii timing ? data transmitted from mii ................................................................................ 107 figure 19. phy mode mii timing ? data received from mii ..................................................................................... 108 figure 20. phy mode mii timing ? data transmitted from mii ................................................................................. 108 figure 21 . rmii timing ? data received from rmii .................................................................................................. 109 figure 22 . rmii timing ? data transmitted to rmii .................................................................................................. 109 figure 23 . spi input timing ....................................................................................................................................... 110 figure 24 . spi output timing ..................................................................................................................................... 111 figure 25 : auto - negotiation timing ........................................................................................................................... 112 figure 26. mdc/mdio timing .................................................................................................................................... 113 figure 27. reset timing ............................................................................................................................................. 114 figure 28 . recommended reset circuit .................................................................................................................... 115 figure 29 . recommended circuit for interfacing with cpu/fpga reset .................................................................. 115 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 12 r evision 1. 6 list of tables table 1. mdi/mdi - x pin definitions ............................................................................................................................. 26 table 2. internal function block status ........................................................................................................................ 29 table 3. port 5 phy p5 - mii/rmii signals .................................................................................................................... 36 table 4. switch mac5 mii signals ............................................................................................................................... 37 table 5. po rt 5 mac5 sw5 - rmii connection .............................................................................................................. 39 table 6. sni signals ..................................................................................................................................................... 40 table 7. tail tag rules ................................................................................................................................................ 44 table 8. fid+da look - up in the vlan mode ............................................................................................................. 46 table 9. fid+sa look - up in the vlan mode .............................................................................................................. 46 table 10. spi c onnections .......................................................................................................................................... 49 table 11. mii management interface frame format ................................................................................................... 51 table 12. serial management interface (smi) frame format ..................................................................................... 51 table 13. 100bt rate selection for the rate limit ....................................................................................................... 89 table 14. 10bt rate selection for the rate limit ........................................................................................................ 89 table 15. static mac address table ........................................................................................................................... 91 table 16. vlan table .................................................................................................................................................. 93 table 17. vlan id and indirect registers ................................................................................................................... 94 table 18. dynamic mac address table ...................................................................................................................... 95 table 19. port1 mib counter indirect memory offerts ................................................................................................. 96 table 20. format of ?per port? mib counter ................................................................................................................ 97 table 21. all port dropped packet mib counters ........................................................................................................ 97 table 22. format of ?all dropped packet? mib counter .............................................................................................. 97 table 23. eeprom timing parameters .................................................................................................................... 105 table 24. sni timing parameters .............................................................................................................................. 106 table 25. mac mode mii timing parameters ............................................................................................................ 107 table 26. phy mode mii timing parameters ............................................................................................................ 108 table 27. rmii timing parameters ............................................................................................................................ 109 table 28. spi input timing parameters ..................................................................................................................... 110 table 29. spi output timing parameters .................................................................................................................. 111 table 30. auto - negotiation timing parameters ......................................................................................................... 112 table 31. mdc/mdio ty pical timing parameters ..................................................................................................... 113 table 32. reset timing parameters .......................................................................................................................... 114 table 33. transformer selection criteria ................................................................................................................... 116 table 34. qualified magnetic vendors ....................................................................................................................... 116 table 35. typical reference crystal characteristics ................................................................................................. 116 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 13 r evision 1. 6 pin configu ration txm 5 vddat fxsd 3 txp 5 33 34 35 36 37 38 ksz 8895 mq / rq / fmq ( top view ) nc pmrxdv / pmcrsdv nc nc nc nc nc nc pwrdn _ n intr _ n gndd vddc pmtxen pmtxd 3 pmtxd 2 pmtxd 1 pmtxd 0 pmtxer pmtxc / pmrefclk gndd pmrxd 1 vddio pmrxc pmrxd 3 pmrxd 2 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 64 fxsd 4 led 3 - 1 led 4 - 0 led 3 - 2 sconf 1 scol smrxd 2 vddio smtxc / smrefclk smtxd 0 smtxd 2 smtxen pcol pcrs pmrxer led 4 - 1 led 4 - 2 led 5 - 1 led 5 - 2 vddc gndd sconf 0 scrs smrxd 0 smrxd 1 smrxd 3 smrxdv / smcrsdv smrxc gndd smtxer smtxd 1 smtxd 3 pmrxd 0 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 led 2 - 1 led 2 - 2 vddio gndd led 3 - 0 101 100 99 98 97 led 2 - 0 102 103 gnda led 1 - 0 mdixdis test 2 gnda in _ pwr _ sel ldo _ o nc x 2 x 1 nc scanen testen vddc gndd rst _ n ps 0 ps 1 spis _ n spid / sda spic / scl spiq mdio mdc led 1 - 1 led 1 - 2 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 vddar rxp 1 rxm 1 gnda txp 1 txm 1 vddat rxp 2 rxm 2 rxm 3 txp 3 rxp 4 txm 4 vddar rxm 5 gnda gnda txp 2 txm 2 vddar gnda iset vddat rxp 3 gnda txm 3 vddat rxm 4 gnda txp 4 gnda rxp 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 nc led 5 - 0 128- pin pqfp micrel, inc. ksz8895mq/rq/fmq january 22, 2013 14 r evision 1. 6 pin description pin number pin name type (1) port pin function ( 2 ) 1 mdi - xdis i pd 1 ? 5 disable auto mdi/mdi - x. pd (default) = normal operation. pu = disable auto mdi/mdi - x on all ports. 2 gnda gnd anal og ground. 3 vddar p 1.2v analog v dd . 4 rxp1 i 1 physical receive signal + (differential). 5 rxm1 i 1 physical receive signal - (differential). 6 gnda gnd analog ground. 7 txp1 o 1 physical transmit signal + (differential). 8 txm1 o 1 physica l transmit signal - (differential). 9 vddat p 3.3v analog v dd . 10 rxp2 i 2 physical receive signal + (differential). 11 rxm2 i 2 physical receive signal - (differential). 12 gnda gnd analog ground. 13 txp2 o 2 physical transmit signal + (differ ential). 14 txm2 o 2 physical transmit signal - (differential). 15 vddar p 1.2v analog v dd . 16 gnda gnd analog ground. 17 iset set physical transmit output current. pull - down with a 12. 4 k 1% resistor. 18 vddat p 3.3v analog v dd . 19 rxp3 i 3 physical receive signal + (differential). 20 rxm3 i 3 physical receive signal - (differential). 21 gnda gnd analog ground. 22 txp3 o 3 physical transmit signal + (differential). 23 txm3 o 3 physical transmit signal ? (differential). 24 vddat p 3.3v analog v dd . 25 rxp4 i 4 physical receive signal + (differential). 26 rxm4 i 4 physical receive signal - (differential). 27 gnda gnd analog ground. 28 txp4 o 4 physical transmit signal + (differential). 29 txm4 o 4 physical transmit signal - (differential). 30 gnda gnd analog ground. 31 vddar p 1.2v analog v dd . 32 rxp5 i 5 physical receive signal + (differential). 33 rxm5 i 5 physical receive signal - (differential). 34 gn da gnd analog ground. 35 txp5 o 5 physical transmit signal + (differential). 36 txm5 o 5 physical transmit signal - (differential). 37 vddat p 3.3v analog v dd . 38 fxsd3 i pd 3 fmq: fiber signal detect pin for port 3 . mq/rq : no connection . micrel, inc. ksz8895mq/rq/fmq january 22, 2013 15 r evision 1. 6 pin description (continued) pin number pin name type (1) port pin function ( 2 ) 39 fxsd4 i pd 4 fmq: fiber signal detect pin for port 4. mq/rq: no connection. 40 nc nc no connect. 41 nc nc no connect. 42 nc nc no connect. 43 nc nc no connect. 44 n c nc no connect. 45 nc nc no connect. 46 nc nc no connect. 47 pwrdn_n i pu full - chip power down. active low. 48 intr_n o pu interrupt. this pin is open - drain output pin . 49 gndd gnd digital ground. 50 vddc p 1.2v digital core v dd . 51 pmtx en ipd 5 phy[5] mii/rmii transmit enable . 52 pmtxd3 ipd 5 mq/fmq: phy[5] mii transmit bit 3 . rq: no connection for rmii. 53 pmtxd2 ipd 5 mq/fmq: phy[5] mii transmit bit 2. rq: no connection for rmii. 54 pmtxd1 ipd 5 phy[5] mii/rmii transmit bit 1 . 5 5 pmtxd0 ipd 5 phy[5] mii/rmii transmit bit 0 . 56 pmtxer ipd 5 mq/fmq: phy[5] mii transmit error. rq: no connection for rmii. 57 pmtxc /pmrefclk i/o 5 mq/fmq: output phy[5] mii transmit clock rq: input phy[5] rmii reference clock , 50mhz 50ppm, the 50mhz clock comes from pmrxc pin 60. 58 gndd gnd digital ground. 59 vddio p 3.3v , 2.5v or 1.8 v digital v dd for digital i/o circuitry. 60 pmrxc i/o 5 mq/fmq: output phy[5] mii receive clock . rq: output phy[5] rmii reference clock , this clock is used when o pposite doesn?t provide rmii 50mhz clock or the system doesn?t provide an external 50mhz clock for the p5 - rmii interface. 61 pmrxdv /pmcrsdv i pd /o 5 mq/fmq: pmrxdv is for phy[5] mii receive data valid . rq: pmcrsdv is for phy[5] rmii carrier sense/receive d ata valid output . 62 pmrxd3 ipd /o 5 mq/fmq: phy[5] mii receive bit 3. rq: no connection for rmii. strap option: pd (default) = enable flow control . pu = disable flow control. 63 pmrxd2 i pd /o 5 mq/fmq: phy[5] mii receive bit 2 . rq: no connection for rmii . strap option: pd (d efault) = disable back pressure . pu = enable back pressure. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 16 r evision 1. 6 pin description (continued) pin number pin name type (1) port pin function (2) 64 pmrxd1 i pd /o 5 phy[5] mii/rmii receive bit 1 . strap option: pd (default) = d rop excessiv e collision packets. pu = does not drop excessive collision packets. 65 pmrxd0 i pd /o 5 phy[5] mii/rmii receive bit 0 . strap option: pd (default) = disable aggressive back - off algorithm in half - duplex mode . pu = enable for performance enhancement. 66 pm rxer i pd /o 5 mq/fmq:phy[5] mii receive error rq: no connection for rmii strap option: pd (default ) = packet size 1518/1522 bytes . pu = 1536 bytes. 67 pcrs i pd /o 5 mq/fmq: phy[5] mii carrier sense. rq: no connection for rmii. strap option for port 4 onl y. pd (default) = force half - duplex if auto- negotiation is disabled or fails. pu = force full - duplex if auto negotiation is disabled or fails. refer to register 76. 68 pcol i pd /o 5 mq/fmq: phy[5] mii collision detect . rq: no connection. strap option fo r port 4 only. pd (default) = no force flow control, normal operation. pu = force flo w control. refer to register 66. 69 smtxen i pd port 5 switch mii/rmii transmit enable. 70 smtxd3 i pd mq/fmq: port 5 switch mii transmit bit 3. rq: no connection for rmii. 71 smtxd2 i pd mq/fmq: port 5 switch mii transmit bit 2. rq: no connection for rmii. 72 smtxd1 i pd port 5 switch mii/rmii transmit bit 1. 73 smtxd0 i pd port 5 switch mii/rmii transmit bit 0. 74 smtxer i pd mq/fmq: port 5 switch mii transmi t error. rq: no connection for rmii . 75 smtxc /smrefclk i/o mq/fmq: port 5 switch mii transmit clock, input: sw5 - mii mac mode , output: sw5 - mii phy modes. rq: input sw5 - rmii 50mhz +/ - 50ppm reference clock. the 50mhz clock comes from smrxc pin 78 when the device is the clock mode which the device?s clock comes from 25mhz crystal/oscillator from pins x1/x2. or the 50mhz clock comes from external 50mhz clock source when the device is the normal mode which the device?s clock source comes from smtxc pin not fr om x1/x2 pins. 76 gndd gnd digital ground. 77 vddio p 3.3v , 2.5v or 1.8 v digital v dd for digital i/o circuitry. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 17 r evision 1. 6 pin description (continued) pin number pin name type (1) port pin function (2) 78 smrxc i/o mq/fmq : port 5 switch mii receive clock , input : sw5 - mii mac mode, output: sw5 - mii phy mode . rq: output sw5 - rmii 50mhz clock , this clock is used when opposite doesn?t provide rmii reference clock or the system doesn?t provide an external 50mhz clock for the rmii interface. 79 smrxdv /smcrsdv i pd /o mq/ fmq: smrxdv is for switch mac5 mii receive data valid. rq: smcrsdv is for mac5 rmii carrier sense/receive data valid output . 80 smrxd3 ipd /o mq/fmq: port 5 switch mii receive bit 3. rq: no connection for rmii strap option: pd (default) = disable switc h sw5 - mii full - duplex flow control pu = enable switch sw5 - mii full - duplex flow control. 81 smrxd2 ipd /o mq/fmq: port 5 switch mii receive bit 2. rq: no connection for rmii strap option: pd (default) = switch sw5 - mii in full - duplex mode; pu = switch s w5 - mii in half - duplex mode. 82 smrxd1 ipd /o port 5 switch mii/rmii receive bit 1. strap option: pd (default) = port 5 switch sw5 - mii in 100mbps mode . pu = switch sw5 - mii in 10mbps mode. 83 smrxd0 ipd /o port 5 switch mii/rmii receive bit 0 . strap op tion: led mode pd (default) = mode 0; pu = mode 1. see ?register 11.? mode 0, link at : 100/full ledx[2,1,0] = 0, 0, 0 100/half ledx[2,1,0] = 0, 1, 0 10/full ledx[2,1,0] = 0, 0, 1 10/half ledx[2,1,0] = 0, 1, 1 mode 1, link at : 100/f ull ledx[2,1,0] = 0 , 1, 0 100/half ledx[2,1,0] = 0, 1, 1 10/full ledx[2,1,0] = 1, 0, 0 10/half ledx[2,1,0] = 1, 0, 1 mode 0 mode 1 ledx_2 lnk/act 100lnk/act ledx_1 fulld/col 10lnk/act ledx_0 speed full duplex 84 scol ipd /o mq/fmq: port 5 switch mii collision detect , input: sw5 - mii mac modes , output: sw5 - mii phy modes. rq: no connection for rmii 85 scrs ipd /o mq/fmq: port 5 switch mii modes carrier sense , input: sw5 - mii mac modes , output: sw5 - mii phy modes. rq: no connection for rmii micrel, inc. ksz8895mq/rq/fmq january 22, 2013 18 r evision 1. 6 pin descrip tion (continued) pin number pin name type (1) port pin function ( 2 ) 86 sconf1 i pd pin s 91, 86, and 87 are d ual mii/rmii configuration pin s for the port 5 mac5 mii/rmii and phy[5] mii /rmii . sw5 - mii supports both mac mode and phy modes. p5 - mii supports phy mode only. see pins configuration below. pin# (91, 86, 87) port 5 switch mac5 sw5 - mii/rmii port5 phy5 p5 - mii /rmii 000 disable, otri disable, otri 001 phy mode mii, or rmii disable, otri 010 mac mode mii, or rmii disable, otr i 011 phy mode sni disable, otri 100 disable (default) disable (default) 101 phy mode mii or rmii p5 - mii/rmii 110 mac mode mii or rmii p5 - mii/rmii 111 phy mode sni p5 - mii/rmii 87 sconf0 i pd dual mii/rmii configuration pin. see pin 86 descriptions. 88 gndd gnd digital ground. 89 vddc p 1.2v digital core v dd . 90 led5 -2 ipu /o 5 led indicator 2. strap option: a ging setup. see ?aging? secti on. pu (default) = aging enable pd = aging disable. 91 led5 -1 ipu /o 5 led indicator 1. strap option: pu (default): enable phy[5] mii i/f. pd: tristate all phy[5] mii output. see ?pin 86 sconf1.? 92 led5 -0 ipu /o 5 led indicator 0. strap option for port 4 only. pu (default) = enable auto - negotiation. pd = disable auto - nega tiation. strap to register76 bit[7] . 93 led4 -2 i pu /o 4 led indicator 2. 94 led4 -1 ipu /o 4 led indicator 1. 95 led4 -0 ipu /o 4 led indicator 0. strap option: pu (default) = normal mode. pd = energy detection mode (edpd mode) strap to register 14 bits [4:3] 96 led3 -2 ipu /o 3 led indicator 2. 97 led3 -1 ipu /o 3 led indicator 1. 98 led3 -0 ipu /o 3 led indicator 0. strap option: pu (default) = select i/o drive strength ( 8 ma); pd = select i/o drive strength ( 12 ma). strap to register 132 bit[ 7 - 6 ]. 99 gndd gnd digital ground. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 19 r evision 1. 6 pin description (continued) pin number pin name type (1) port pin function ( 2 ) 100 vddio p 3.3v , 2.5v or 1.8 v digital v dd for digital i/o circuitry. 101 led2 -2 i pu /o 2 led indicator 2. strap option for rq only: pu (default) = s elect the device as clock mode in sw 5 - rmii , 25mhz crystal/oscillator to x1/x2 pins of the device and pins of smrxc and pmrxc output 50mhz clock. pd = select the device as normal mode in sw 5 - rmii. switch m ac5 used only . the input clock from x1/x2 pins is not used, the device?s clock source comes from smtxc/smrefclk pin which the 50mhz reference clock comes from external 50mhz clock source, pmrxc can output 50mhz clock for p5 - rmii interface in the normal mode. 102 led2 -1 i pu /o 2 led indicator 1. strap opti on: for p ort 3 only. pu (default) = enable auto - negotiation. pd = disable auto - negatiation. strap to register60 bit[7]. 103 led2 -0 i pu /o 2 led indicator 0. 104 led1 -2 i pu /o 1 led indicator 2. 105 led1 -1 i pu /o 1 led indicator 1. strap option: for por t 3 only. pu (default) = no force flow control, normal operation. pd = force flow control. strap to register60 bit[4] . 106 led1 -0 i pu /o 1 led indicator 0. strap option for port 3 only. pu (default) = force half - duplex if auto- negotiation is disabled or fails. pd = force full - duplex if auto negotiation is disabled or fails. strap to register60 bit[5]. 107 mdc i pu all switch or phy[5] mii management (miim registers) data clock. or smi interface clock 108 mdio i pu /o all switch or phy[5] mii management (miim registers) data i/o. or smi interface data i/o. features internal pull down to define pin state when not driven. not e: need an external pull - up when driven. 109 spiq i pu /o all spi seria l data output in spi slave mode. not e: need an external pull -up when driven. 110 spic/scl i pu /o all (1) input clock up to 2 5mhz in spi slave mode , (2) output clock at 61khz in i 2 c master mode. see ?pin 113.? not e: need an external pull - up when driven. 111 sspid/sda i pu /o all (1) serial data input in spi slave mode; (2) serial data input/output in i 2 c master mode. see ?pin 113.? not e: need an external pull - up when driven. 112 spis_n i pu all active low. (1) spi data transfer start in spi slave mode. when spis_n is high, the ksz8895mq/rq/fmq is deselected and spiq is held in high impedance state, a high -to - low transition to initiate the spi data transfer. (2) not used in i 2 c master mode. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 20 r evision 1. 6 pin description (continued) pin number pin name type (1) port pin function ( 2 ) 113 ps1 i pd serial bus configuration pin. for thi s case, if the eeprom is not present, the ksz8895mq/rq/fmq will start itself with the ps[1.0] = 00 default register values. pin configuration serial bus configuration ps[1.0] = 00 i 2 c master mode for eeprom ps[1.0] = 01 smi interface mode ps[1.0] = 10 spi slave mode for cpu interface ps[1.0] = 11 factory test mode (bist) 114 ps0 i pd serial bus configuration pin. see ?pin 113.? 115 rst_n i pu reset the ksz8895mq/rq/fmq device . active low. 116 gndd gnd digital ground. 117 vddc p 1.2v digital core v dd . 118 testen i pd nc for normal operation. factory test pin. 119 scanen i pd nc for normal operation. factory test pin. 120 nc nc no connect. 121 x1 i 25mhz crystal clock connection/or 3.3v o scillator input. crystal/ oscilla tor should be 5 0ppm tolerance . 122 x2 o 25mhz crystal clock connection. 123 nc nc no connect. 124 nc nc no connect. 125 ldo_o p when pin126 is pull - up, the internal 1.2v ldo controller is enabled and create s a 1.2v output when using an external fet. when pin126 is pull - down, the pin 125 is tristated. not e: use a 20 0 (approximately) resistor between the source and drain pins on the fet if 3.3v power rail exhibits a slow ramp (>1ms) when us ing this internal 1.2v ldo controller . you can also use an external 1.2v ldo when 3.3v power ramp - up time is slow. 126 in_pwr_sel i pull - up to enable ldo_o of pin 125. pull - down to disable ldo_0. note: use resistors for this pin pull - up and pull - down. 127 gnda gnd analog ground. 128 test2 nc nc for normal operation. factory test pin. not es: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. i pu = input w/internal pull - up. ipd = input w/internal pull - down. ipd /o = input w/internal pull - down during reset, output pin otherwise. ipu /o = input w/internal pull - up during reset, output pin otherwis e. nc = no connect. 2. pu = strap pin pull - up. pd = strap pull - down. otri = output tristated. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 21 r evision 1. 6 pin for strap - in options the ksz8895mq/rq/fmq can function as a managed switch or an unmanaged switch. if no eeprom or micro - controller exists, then the ksz88 95mq/rq/fmq will operate from its default setting. the strap - in option pins can be configure d by external pull - up/down resistors and take effect after power down reset or warm reset . t he functions are described in the table below. pin # pin name pu/pd (1) description (1) 1 mdi - xdis i pd disable auto mdi/mdi - x. strap option: pd = (default) = normal operation. pu = disable auto mdi/mdi - x on all ports. 62 pmrxd3 i pd /o phy[5] mii receive bit 3. strap option: pd (default) = enable flow control; pu = disable f low control. 63 pmrxd2 i pd /o phy[5] mii receive bit 2. strap option: pd (default) = disable back pressure; pu = enable back pressure. 64 pmrxd1 i pd /o phy[5] mii receive bit 1. strap option: pd (default) = drop excessive collision packets; pu = does not drop excessive collision packets. 65 pmrxd0 i pd /o phy[5] mii receive bit 0. strap option: pd (default) = disable aggressive back - off algorithm in half - duplex mode; pu = enable for performance enhancement. 66 pmrxer i pd /o phy[5] mii receive error. strap option: pd (default) = 1522/1518 bytes; pu = packet size up to 1536 bytes. 67 pcrs i pd /o phy[5] mii carrier sense strap option for port 4 only. pd (default) = force half - duplex if auto- negotiation is disabled or fails. pu = force full - duplex if auto - negotiation is disabled or fails. refer to register 76. 68 pcol i pd /o phy[5] mii collision detect strap option for port 4 only. pd (default) = no force flow control. pu = force flow control. refer to register 66. 80 smrxd3 i pd /o switch mii rece ive bit 3. strap option: pd (default) = disable switch sw5 - mii full - duplex flow control; pu = enable switch sw5 - mii full - duplex flow control. 81 smrxd2 i pd /o switch mii receive bit 2. strap option: pd (default) = switch sw5 - mii in full - duplex mode; pu = switch sw5 - mii in half - duplex mode. 82 smrxd1 ipd /o switch mii receive bit 1. strap option: pd (default) = switch sw5 - mii in 100mbps mode. pu = switch mii in 10mbps mode. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 22 r evision 1. 6 pin for strap - in options (continued) pin # pin name pu/pd (1) descriptio n (1) 83 smrxd0 i pd /o switch mii receive bit 0. strap option: led mode pd (default) = mode 0; pu = mode 1. see ?register 11.? mode 0 mode 1 ledx_2 lnk/act 100lnk/act ledx_1 fulld/col 10lnk/act ledx_0 speed fulld 86 sconf1 i pd pin 91,86,8 7 are d ual mii/rmii configuration pin s for the port 5 mac 5 mii/rmii and phy[5] mii /rmii . sw5 - mii suppor ts both mac mode and phy modes. p5 - mii supports phy mode only. see pins configuration below. pins [91, 86, 87] port 5 mac 5 switch sw5 - mii port 5 ph y [5] mii /rmii p5 - mii /rmii 000 disable, otri disable, otri 001 phy mode mii or rmii disable, otri 010 mac mode mii or rmii disable, otri 011 phy mode sni disable, otri 100 disable disable 101 phy mode mii or rmii p5 - mii/rmii 110 mac mode mii or rmii p5 - mii/rmii 111 phy mode sni p5 - mii/rmii 87 sconf0 i pd dual mii/rmii configuration pin. see pin 86 description. 90 led5 -2 i pu /o led 5 indicator 2. strap option: aging setup. see ?aging? section pu (default) = aging enab le; pd = aging disable. 91 led5 -1 i pu /o led 5 indicator 1. strap option: pu (default): enable phy[5] mii i/f. pd: tristate all phy[5] mii output. see ?pin 86 sconf1.? 92 led5 -0 ipu /o led 5 indicator 0. strap option for p ort 4 only. pu (default) = enable auto - negotiation. pd = disable auto - negatiation. strap to register76 bit[7] . 95 led4 -0 ipu /o led indicator 0. strap option: pu (default) = normal mode. pd = energy detection mode (edpd mode). strap to register 14 bits[4:3]. 98 led3 -0 ipu /o led 3 indicator 0. strap option: pu (default) = select i/o current drive strength ( 8 ma); pd = select i/o current drive strength ( 12 ma). strap to register1 32 bit[7:6]. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 23 r evision 1. 6 pin # pin name pu/pd (1) description (1) 101 led2 -2 i pu /o led 2 indicator 2. strap opt ion for ksz8895 rq only: pu (default) = select the device as clock mode in rq sw 5 - rmii , 25mhz crystal to x1/x2 pins of the device and refclk output 50mhz clock. pd = select the device as normal mode in sw 5 - rmii. switch m ac5 used only . the input clock is useless from x1/x2 pin, the device?s clock comes from smtxc/smrefclk pin, 50mhz reference clock from external 50mhz clock source. 102 led2 -1 ipu /o led 2 indicator 1. strap option for p ort 3 only. pu (default) = enable auto - negotiation. pd = disable auto - n egatiation. strap to register60 bit[7 ]. 105 led1 -1 ipu /o led 1 indicator 1. strap option for p ort 3 only. pu (default) = no force flow control, normal operation. pd = force flow control. strap to register50 bit[4] . 106 led1 -0 ipu /o led 1 indicator 0. st rap option for p ort 3 only. pu (default) = force half - duplex if auto- negotiation is disabled or fails. pd = force full - duplex if auto negotiation is disabled or fails. strap to register60 bit[5] . 113 ps1 ipd serial bus configuration pin. for this ca se, if the eeprom is not present, the ksz8895mq/rq/fmq will start itself with the ps[1:0] = 00 default register values . pin configuration serial bus configuration ps[1:0] = 00 i 2 c master mode for eeprom ps[1:0] = 01 smi interface mode ps[1:0] = 10 spi slave mode for cpu interface ps[1:0] = 11 factory test mode (bist) 114 ps0 ipd serial bus configuration pin. see ?pin 113.? 128 test2 nc nc for normal operation. factory test pin. not es: 1. nc = no connect. i pd = input w/ internal pull - down. ipd /o = input w/internal pull - down duri ng reset, output pin otherwise. ipu /o = input w/internal pull - up during reset, output pin otherwise. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 24 r evision 1. 6 introduction the ksz8895mq/rq/fmq contains five 10/100 physical layer transceivers and five m edia access control (mac) units with an integrated layer 2 managed switch. the device runs in three modes. the first mode is as a five - port integrated switch. the second is as a five - port switch with the fifth port decoupled from the physical port. in this mode, access to the fifth mac is provided through a media independent interface ( mii/rmii ). this is useful for implementing an integrated broadband router. the third mode uses the dual mii/rmii feature to recover the use of the fifth phy. this allows the additional broadband gateway configuration, where the fifth phy may be accessed through the p5 - mii/rmii port. the ksz8895mq/rq/fmq has the flexibility to reside in a managed or unmanaged design. in a managed design, a host processor has complete control of the ksz8895mq/rq/fmq via the spi bus, or the mdc/mdio interface. an unmanaged design is achieved through i/o strapping or eeprom programming at system reset time. on the media side, the ksz8895mq/rq/fmq supports ieee 802.3 10base - t, 100base - tx on all copp er ports with auto mdi/mdix. the ksz8895fmq supports 100base - fx on port 3 and port 4. the ksz8895mq/rq/fmq can be used as a fully managed five - port switch or hook ed up to a microprocessor by its sw - mii/rmii interfaces for any application solutions. physica l signal transmission and reception are enhanced through the use of patented analog circuitry that makes the design more efficient and allows for reduced power consumption and smaller chip die size. m ajor enhancements from the ks8895ma/fq to the ksz8895mq/ fmq include more host interface options, a dual - s witch mac5 mii and phy5 mii interfaces with other options, rmii from part of the ksz8895rq, tag and port - based vlan, rapid spanning tree support, igmp snooping support, port mirroring support , more flexible rate limiting , and new filtering functionality. functional overview: physical layer transceiver 100base - tx transmit the 100base - tx transmit function performs parallel - to - serial conversion, 4b/5b coding, scrambling, nrz - to - nrzi conversion, mlt3 encoding an d transmission. the circuit starts with a parallel - to - serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding followed by a scrambler. the serialized data is further converted from nrz - to - nrzi format, and then transmitted in mlt3 current output. the output current is set by an external 1% 12.4k? resistor for the 1:1 transformer ratio. it has a typical rise/fall time of 4ns and complies with the ansi tp - pmd s tandard regarding amplitude balance, overshoot, and timing jitter. the wave - shaped 10base - t output is also incorporated into the 100base - tx transmitter. 100base - tx receive the 100base - tx receiver function performs adaptive equalization, dc restoration, mlt 3 - to - nrzi conversion, data and clock recov ery, nrzi - to - nrz conversion, de scrambling, 4b/5b decoding, and serial - to - parallel conversion. the receiving side starts with the equalization filter to compensate fo r inter symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. in this design, the variable equalizer will make an initial estimation based o n comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. this is an ongoing process and can self - adjust against environmental changes such as temperature variations. the equalized signal then g oes through a dc restoration and data conversion block. the dc restoration circuit is used to compensate for the effect of baseline wander and improve the dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the sl icing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. the signal is then sent through the de - scrambler fol lowed by the 4b/5b decoder. finally, the nrz serial data is converted to the mii format and provided as the input data to the mac. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 25 r evision 1. 6 pll clock synthesizer the ksz8895mq/rq/fmq generates 125mhz, 83mhz, 41mhz, 25mhz and 10mhz clocks for system timing. interna l clocks are generated from an external 25mhz crystal or oscillator. scrambler/des crambler (100base - tx only) the purpose of the scrambler is to spread the power spectrum of the signal in order to reduce emi and baseline wander. the data is scrambled throug h the use of an 11 - bit wide linear feedback shift register (lfsr). this can generate a 2047 - bit non - repetitive sequ ence. the receiver will then de scramble the incoming data stream with the same sequence at the transmitter. 100base - fx operation 100base - fx o peration is very similar to 100base - tx operati on except that the scrambler/de scrambler and mlt3 encoder/decoder are bypassed on transmission and reception. in this mode , the auto - negotiation feature is bypassed since there is no standard that supports fibe r auto - negotiation. 100base - fx signal detection the physical port runs in 100base - fx fiber mode for the port 3 and p ort 4 of the ksz8895fmq. this signal is internally referenced to 1.2v. the fiber module interface should be set by a voltage divider such th at fxsdx ?h? is above this 1.2v reference, indicating signal detect, and fxsdx ?l? is below the 1.2v reference to indicate no signal. there is no auto - negotiation for 100base - fx mode, the ports must be forced to either full or half - duplex for the fiber por ts. not e that strap - in options support p ort 3 and p ort 4 to disable a uto - negotiation, force 100base - fx speed, force duplex mode , and force flow control for ksz8895fmq with unmanaged mode. 100base - fx f ar e nd f ault f ar end fault occurs when the signal detect ion is logically false from the receive fiber module. when this occurs, the transmission side signals the other end of the link by sending 84 1s followed by a zero in the idle period between frames. 10base - t transmit the output 10base - t driver is incorpora ted into the 100base - t driver to allow transmission with the same magnetics. they are internally wave - shaped and pre - emphasized into outputs with a typical 2.3v amplitude. the harmonic contents are at least 27db below the fundamental when driven by an all - ones manchester - encoded signal. 10base - t receive on the receive side, input buffer and level detecting squelch circuits are employed. a differential input receiver circuit and a pll perform the decoding func tion. the manchester - encoded data stream is separ ated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400mv or with short pulsewidths in order to prevent noises at the rxp or rxm input from falsely triggering the decoder. when the input exceeds the squelch limit, t he pll locks onto the incoming signal and the ksz8895mq/rq/fmq decodes a data frame. the receiver clock is maintained active during idle periods in between data reception. mdi/mdi - x auto crossover to eliminate the need for crossover cables between similar devices, the ksz8895mq/rq/fmq supports hp auto mdi/mdi - x and ieee 802.3u standard mdi/mdi - x auto crossover. hp auto mdi/mdi - x is the default. the auto - sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the ksz8895mq/rq/fmq device. this feature is extremely useful when end users are unaware of cable types, and also, saves on an additional uplink configuration connection. the auto - crossover feature can be disabled through the port control registers, o r miim phy registers. the ieee 802.3u standard mdi and mdi - x definitions are: micrel, inc. ksz8895mq/rq/fmq january 22, 2013 26 r evision 1. 6 mdi mdi -x rj - 45 pins signals rj - 45 pins signals 1 td+ 1 rd+ 2 td - 2 rd- 3 rd+ 3 td+ 6 rd- 6 td - table 1 . mdi/mdi - x pin definitions straight cable a straight cable connects an mdi device to an mdi - x device, or an mdi - x device to an mdi device. the following diagram depicts a typical straight cable connection between a nic card (mdi) and a switch, or hub (mdi - x). figure 1 . typical straight cable connection micrel, inc. ksz8895mq/rq/fmq january 22, 2013 27 r evision 1. 6 crossover cable a crossover cable connects an mdi device to a not her mdi device, or an mdi - x device to a not her mdi - x device. the following diagram shows a typical crossover cable connection between two switches or hubs (tw o mdi - x devices). figure 2 . typical crossover cable connection auto - negotiation the ksz8895mq/rq/fmq conforms to the auto - negotiation protocol as described by the 802.3 committee. auto - negotiation allows unshielded twisted pair ( utp) link partners to select the highest common mode of operation. link partners advertise their capabilities to each other, and then compare their own capabilities with those they received from their link partners. the highest speed and duplex setting tha t is common to the two link partners is sele cted as the mode of operation. auto - negotiation is supported for the copper ports only. the following list shows the speed and duplex operation mode from highe st to lowest. ? highest : 100base - tx, full - duplex ? high : 100base - tx, half - duplex ? low: 10base - t, full - duplex ? lowest: 10base - t, half - duplex if auto - negotiation is not supported or the ksz8895mq/rq/fmq link partner is forced to bypass auto - negotiation, the ksz8895mq/rq/fmq sets its operating mode by observing the signal at its receiver. this is known as parallel detection, and allows the ksz8895mq/rq/fmq to establish link by listening for a fixed signal protocol in the absence of auto - negotiation advertisement protocol. the auto - negotiation link up pr ocess is shown in the following flow chart. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 28 r evision 1. 6 figure 3 . auto - negotiation micrel, inc. ksz8895mq/rq/fmq january 22, 2013 29 r evision 1. 6 on - chip termination r esistors the ksz8895mq/rq/fmq reduces the board cost and simplifies the board layout by using on - chip termination resistors for all ports and rx/tx differential pairs without the external termination resistors. the combination of the on- chip termination and internal biasing will save about 500 to 1000mw in power consumption as compare d to using external biasing and termination resistor s, and the transformer will not consume power any more. t he center tap of the transformer does not need to be tied to the analog power and do es not tie the center taps together between rx and tx pairs for its application. internal 1.2v ldo controller the k sz8895mq/rq/fmq reduces board cost and simplifies board layout by integrating a n internal 1.2v ldo controller to drive a low cost mosfet to supply the 1.2v core power voltage for a single 3.3v power supply solution . the internal 1.2v ldo controller can be disabled by pin 126 in_pwr_sel pull - down in order to use an external 1.2v ldo. functional overview: power management the ksz8895mq/rq/fmq supports a full chip hardware power down mode. when the pwrdn pin 47 is internally activated low (pin pwrdn = 0) , the entire chip is powered down. if this pin is de - asserted, the chip will be reset internal ly . the ksz8895mq/rq/fmq can also use multiple power level s of 3.3v, 2.5v or 1.8v for vddio to support different i/o voltage. the ksz8895mq/rq/fmq supports enhanced p ower management in a low power state , with energy detection to ensure low power dissipation during device idle periods. there are five operation modes under the power management function which are controlled by the register 14 bit [4:3] and the port r egiste r control 13 bit 3 as shown below: register 14 bit [ 4 : 3 ] = 00 normal operation mode register 14 bit [ 4 : 3 ] = 01 energy detect mode register 14 bit [ 4 : 3 ] = 10 soft power down mode register 14 bit [ 4 : 3 ] = 11 power saving mode the port register 29, 45 , 61, 77, 93 control 13 bit 3 = 1 are for the port based power - down mode . table 2 indicates all internal function blocks ? status under four different power management operation modes. ksz8895mq/rq/fmq function blocks power management operation modes normal mode powe r saving mode energy detect mode soft power down mode internal pll clock enabled enabled disabled disabled tx/rx phy enabled rx unused block disabled energy detect at rx disabled mac enabled enabled disabled disabled host interface enabled enabled disa bled disabled table 2 . internal function block status normal operation mode this is the default setting bit [ 4 : 3 ] = 00 in r egister 14 after chip power - up or hardware reset. when ksz8895mq/rq/fmq is in normal operation mode, all pll clocks are running, phy and mac are on , and the host interface is ready for cpu read or write. during normal operation mod e, the host cpu can set the bit [ 4 : 3 ] in r egister 14 to change the current normal operation mode to any one of the other three power m anagement operation modes. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 30 r evision 1. 6 energy detect mode e nergy detect mode provides a mechanism to save more power than in the normal operation mode when the ksz8895 mq/fmq port is not connected to an active link partner. in this mode, the device will save more powe r when the cables are unplugged . if the cable is not plugged in , the device can automatically enter a low power state ? the energy detect mode. in this mode, the device will keep transmitting 120ns width pulses at 1 pulse/s rate. once activity resumes due to plugging a cable in or attempting by the far end to establish link, the device can automatically power up to normal power state in energy detect mode. energy detect mode consists of two states, normal power state and low power state. while in low power st ate, the device reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. the energy detect mode is entered by setting bit [ 4 : 3 ] = 01 in register 14 . when the ksz8895 mq/fmq is in this mode, it will monitor the cable energy. if there is no energy on the cable for a time longer than the pre - configured value at bit [7:0] go - sleep time in register 15 , ksz8895 mq/fmq will go into low power state. when ksz8895 mq/fmq is in low power state, it will keep monitoring the ca ble energy. once the energy is detected from the cable , the device will enter normal power state . when the device is at normal power state, it is able to transmit or receive packet from the cable. soft power down mode the soft power down mode is entered by setting bit [4:3] = 10 in register 14 . when ksz8895mq/rq/fmq is in this mode, all pll clocks are disabled, also all of phys and the macs are off. any dummy host access will wake - up this device from current soft power down mode to normal operation mode and internal reset will be issued to make all internal registers go to the default values. power saving mode the power saving mode is entered when auto - negotiation mode is enabled, the c able is d isconnected, and by setting bit [4:3] = 11 in register 14 . when ks z8895mq/rq/fmq is in this mode, all pll clocks are enabled, mac is on, all internal register value s will not change, and the host interface is ready for cpu read or write. in this mode, it mainly controls the phy transceiver on or off , based on line status to achieve power saving. the phy continues to transmit, only turn ing off the unused receiver block. once activity resumes , due to plugging a cable or attempting by the far end to establish link, the ksz8895mq/rq/fmq can automatically enable the phy to pow er up to normal power state from power saving mode. during power saving mode, the host cpu can set bit [4:3] in register 14 to change the current power saving mode to any one of the other three power management operation modes. port - based power down mode in addition, t he ksz8895mq/rq/fmq features a per - port power down mode. to save power, a phy port that is not in use can be powered down via the port registers control 13 bit 3, or miim phy registers 0 bit 11. functional overview: switch core address look - up the internal look - up table stores mac addresses and their associated information. it contains a 1k unicast address table plus switching information. the ksz8895mq/rq/fmq is guaranteed to learn 1k addresses and distinguishes itself from a hash - based look - up table, which , depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. learning the internal look - up engine updates its table with a new entry if the following conditions are met: ? the recei ved packet?s source address (sa) does not exist in the look - up table. ? the received packet is good; the packet has no receiving errors and is of legal length. the look - up engine inserts the qualified sa into the table, along with the port number and time s tamp. if the table is full, the last entry of the table is deleted first to make room for the new entry. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 31 r evision 1. 6 migration the internal look - up engine also monitors whether a station is moved. if this occurs, it updates the table accordingly. migration happens wh en the following conditions are met: ? the received packet?s sa is in the table but the associated source port information is different. ? the received packet is good; the packet has no receiving errors and is of legal length. the look - up engine will update t he existing record in the table with the new source port information. aging the look - up engine will update the time stamp information of a record whenever the corresponding sa appears. the time stamp is used in the aging process. if a record is not updated for a period of time, the look - up engine will remove the record from the table. the look - up engine constantly performs the aging process and will continuously remove aging records. the aging period is 300 +/ - 75 seconds. this feature can be enabled or dis abled through register 3 or by external pull - up or pull - down resistors on led[5][2]. see ?register 3? section. forwarding the ksz8895mq/rq/fmq will forward packets using an algorithm that is depicted in the following flowcharts. figure 6 shows stage one of the forwarding algorithm where the search engine looks up the vlan id, static table, and dynamic table for the destination address, and comes up with ?port to forward 1? (ptf1). ptf1 is then further modified by the spanning tree, igmp snooping, port mirro ring, and port vlan processes to come up with ?port to forward 2? (ptf2), as shown in figure 7. this is where the packet will be sent. ksz8895mq/rq/fmq will not forward the following packets : ? error packets. these include framing errors, fcs errors, alignm ent errors, and illegal size packet errors. ? 802.3x pause frames. the ksz8895mq/rq/fmq will intercept these packets and perform the appropriate actions. ? ?local? packets. based on destination address (da) look - up. if the destination port from the look - up tab le matches the port where the packet was from, the packet is defined as ?local.? switching engine the ksz8895mq/rq/fmq features a high - performance switching engine to m ove data to and from the mac?s packet buffers. it operates in store and forward mode, wh ile the efficient switching mechanism reduces overall latency. the ksz8895mq/rq/fmq has a 64kb internal frame buffer. this resource is shared between all five ports. there are a total of 512 buffers available. each buffer is sized at 128b. media access con troller (mac) operation the ksz8895mq/rq/fmq strictly abides by ieee 802.3 standards to maximize compatibility. inter - packet gap (ipg) if a frame is successfully transmitted, the 96 - bit time ipg is measured between the two consecutive mtxen. if the current packet is experiencing collision, the 96 - bit time ipg is measured from mcrs and the next mtxen. backoff algorithm the ksz8895mq/rq/fmq implements the ieee st andar d 802.3 binary exponential back off algorithm, and optional ?aggressive mode? back off. after 1 6 collisions, the packet will be optionally dropped , depending on the chip configuration in register 3. see ?register 3.? late collision if a transmit packet experiences collisions after 512 - bit times of the transmission, the packet will be dropped. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 32 r evision 1. 6 illeg al frames the ksz8895mq/rq/fmq discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in register 4. for special applications, the ksz8895mq/rq/fmq can also be programmed to accept frames up to 1916 bytes in register 4. since the ksz8895mq/rq/fmq supports vlan tags, the maximum sizing is adjusted when these tags are present. flow control the ksz8895mq/rq/fmq supports standard 802.3x flow control frames on both transmit and receive sides. on the receive side, if the ksz889 5mq/rq/fmq receives a pause control frame, the ksz8895mq/rq/fmq will not transmit the next normal frame until the timer, specified in the pause control frame, expires. if a not her pause frame is received before the current timer expires, the timer will be u pdated with the new value in the second pause frame. during this period (being flow controlled), only flow control packets from the ksz8895mq/rq/fmq will be transmitted. on the transmit side, the ksz8895mq/rq/fmq has intelligent and efficient ways to deter mine when to invoke flow control. the flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. the ksz8895mq/rq/fmq flow controls a port that has just received a pac ket if the destination port resource is busy. the ksz8895mq/rq/fmq issues a flow control frame (xoff), containing the maximum pause time defined in ieee standard 802.3x. once the resource is freed up, the ksz8895mq/rq/fmq sends out the other flow control f rame (xon) with zero pause time to turn off the flow control (turn on transmission to the port). a hysteresis feature is also provided to prevent over - activation and deactivation of the flow control mechanism. the ksz8895mq/rq/fmq flow controls all ports i f the receive queue becomes full. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 33 r evision 1. 6 figure 4 . destination address lookup flow chart, stage 1 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 34 r evision 1. 6 figure 5 . destination address resolution flow chart, stage 2 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 35 r evision 1. 6 the ksz8895mq/rq/fmq will not forward the follo wing packets: 1. error packets these include framing errors, frame check sequence (fcs) errors, alignment errors, and illegal size packet errors. 2. ieee802.3x pause frames ksz8895mq/rq/fmq intercepts these packets and performs full duplex flow control according ly. 3. "local" packets based on destination address (da) lookup , i f the destination port from the lookup table matches the port from which the packet originated, the packet is defined as "local." half - duplex back pressure the ksz8895mq/rq/fmq also provides a half - duplex back pressure option ( not e: this is not in ieee 802.3 standards). the activation and deactivation conditions are the same as the ones given for full - duplex mode. if back pressure is required, the ksz8895mq/rq/fmq sends preambles to defer the ot her station's transmission (carrier sense deference). to avoid jabber and excessive deference as defined in ieee 802.3 standard s , after a certain period of time, the ksz8895mq/rq/fmq discontinues carrier sense but raises it quickly after it drops packets t o inhibit other transmissions. this short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in a carrier sense - deferred state. if the port has packets to send during a back pressure situation, the carrier sense - type back pressure is interrupted and those packets are transmitted instead. if there are no more packets to send, carrier sense - type back pressure becomes active again until switch resources are free. if a collision occurs, the binary expon ential backoff algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. to ensure no packet loss in 10base - t or 100base - tx half - duplex modes, th e user must enable the following: ? aggressive backoff (register 3, bit 0) ? no excessive collision drop (register 4, bit 3) ? back pressure (register 4, bit 5) these bits are not set as the default because this is not the ieee standard. broadcast storm protect ion the ksz8895mq/rq/fmq has an intelligent option to protect the switch system from receiving too many broadcast packets. broadcast packets are normally forwarded to all ports except the source port and thus use too many switch resources (bandwidth and av ailable space in transmit queues). the ksz8895mq/rq/fmq has the option to include ?multicast packets? for storm control. the broadcast storm rate parameters are programmed globally and can be enabled or disabled on a per port basis. the rate is based on a 50ms (0.05s) interval for 100bt and a 500ms (0.5s) interval for 10bt. at the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of bytes during the interval. the rate definition is described i n registers 6 and 7. the default setting for registers 6 and 7 is 0x4a (74 decimal). this is equal to a rate of 1%, calculated as follows: 148,80 frames/sec x 50ms (0.05s) /interval x 1% = 74 frames/interval (approx.) = 0x4a micrel, inc. ksz8895mq/rq/fmq january 22, 2013 36 r evision 1. 6 mii interface operation the media - independent interface (mii) is specified by the ieee 802.3 committee and provides a common interface between physical layer and mac layer devices. the ksz8895mq/rq/fmq provides two such interfaces. the p5 - mii interface is used to connect to the fifth phy, where as the sw - mii interface is used to connect to the fifth mac. each of these mii interfaces contains two distinct groups of signals, one for transmission and the other for receiving. port 5 phy 5 p5 - mii /rmii interface the media independent interf ace (mii) is specified by the ieee 802.3 committee and provides a common interface between the physical layer and mac layer devices. the reduced media independent interface (rmii) specifies a low pin count mii . the ksz8895mq/rq/fmq provides two such interf aces for mac5 and phy5. the p ort 5 phy5 p5 - mii/rmii interface is used to connect to the fifth phy, where as the sw - mii/rmii interface is used to connect to the fifth mac. the ksz8895 mq/fmq support p5 - mii, the ksz8895rq supports p5 - rmii. each of these mii/r mii interfaces contains two distinct groups of signals, one for transmission and the other for receiving. table 3 describes the signals used in the phy[5] p5 - mii/rmii interface. the p5 - mii interface operates in phy mode only. mii signal description ksz889 5 mq/fmq p5 - mii ksz8895 mq/fmq mii signal type ksz8895rq p5 - rmii ksz8895 rq rmii signal type mtxen transmit enable pmtxen i pmtxen i mtxer transmit error pmtxer i mtxd3 transmit data bit 3 pmtxd[3] i mtxd2 transmit data bit 2 pmtxd[2] i mtxd1 trans mit data bit 1 pmtxd[1] i pmtxd[1] i mtxd0 transmit data bit 0 pmtxd[0] i pmtxd[0] i mtxc transmit clock pmtxc o pmrefclk/pmtxc i mcol collision detection pcol o mcrs carrier sense pcrs o mrxdv receive data valid pmrxdv o pmrxdv o mrxer receive e rror pmrxer o pmrxer o mrxd3 receive data bit 3 pmrxd[3] o mrxd2 receive data bit 2 pmrxd[2] o mrxd1 receive data bit 1 pmrxd[1] o pmrxd[1] o mrxd0 receive data bit 0 pmrxd[0] o pmrxd[0] o mrxc receive clock pmrxc o pm r xc o table 3 . port 5 phy p5 - mii/rmii signals micrel, inc. ksz8895mq/rq/fmq january 22, 2013 37 r evision 1. 6 port 5 mac 5 sw5 - mii interface for the ksz8895 mq/fmq t able 4 shows two connection manners : 1. the first is an external mac connects to sw5 - mii phy mode. 2. the second is an external phy connects to sw5 - mii mac mode. please see the pin [91,86,87] description s for configuration details for the mac mode and phy mode . sw 5 - mii works with 25mhz clock for 100base - tx, sw 5 - mii works with 2 . 5mhz clock for 10base - t. ksz8895mq/ fmq phy mode connection ksz8895mq/ fmq mac mode conn ection external mac ksz8895mq/ fmq sw5 - mii signal s type description external phy ksz8895mq/ fmq sw5 - mii signal s type mtxen smtxen input transmit enable mtxen smrxdv output mtxer smtxer input transmit error mtxer not used not used mtxd3 smtxd[3] input tr ansmit data bit 3 mtxd3 smrxd[3] output mtxd2 smtxd[2] input transmit data bit 2 mtxd2 smrxd[2] output mtxd1 smtxd[1] input transmit data bit 1 mtxd1 smrxd[1] output mtxd0 smtxd[0] input transmit data bit 0 mtxd0 smrxd[0] output mtxc smtxc output trans mit clock mtxc smrxc input mcol scol output collision detection mcol scol input mcrs scrs output carrier sense mcrs scrs input mrxdv smrxdv output receive data valid mrxdv smtxen input mrxer not used output receive error mrxer smtxer input mrxd3 smrxd [3] output receive data bit 3 mrxd3 smtxd[3] input mrxd2 smrxd[2] output receive data bit 2 mrxd2 smtxd[2] input mrxd1 smrxd[1] output receive data bit 1 mrxd1 smtxd[1] input mrxd0 smrxd[0] output receive data bit 0 mrxd0 smtxd[0] input mrxc smrxc outp ut receive clock mrxc smtxc input table 4 . switch mac5 mii signals the switch mii interface operates in either mac mode or phy mode for ksz8895mq/ fmq . t hese interfaces are nibble - wide data interfaces , so they run at one- quarter th e network bit rate ( not encoded). additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. likewise, the receive side has indicators that convey when the data is valid and without physical layer error s. for half - duplex operation , there is a signal that indicates a collision has occurred during transmission. not e that the signal mrxer is not provided on the mii - sw interface for phy mode operation and the signal mtxer is not provided on the sw - mii interf ace for mac mode operation. normally mrxer would indicate a receive error coming from the physical layer device. mtxer would indicate a transmit error from the mac device. these signals are not appropriate for this configuration. for phy mode operation wit h an external mac, if the device interfacing with the ksz8895mq/ fmq has an mrxer pin, it should be tied low. for mac mode operation with an external phy, if the device interfacing with the ksz8895mq/ fmq has an mtxer pin, it should be tied low. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 38 r evision 1. 6 port 5 mac 5 s witch sw5 - rmii interface for the ksz8895rq the reduced media independent interface (rmii) specifies a low pin count med ia independent interface (mii). the ksz8895rq supports rmii interface at p ort 5 switch side and provides a common interface at mac 5 la yer in the device, and has the following key characteristics: ? supports 10mbps and 100mbps data rates. ? uses a single 50mhz clock reference (provided internally or externally): in internal mode, the chip provides a reference clock from the smrxc pin to the s mtxc pin and provide s the clock to the opposite clock input pin for rmii interface . i n external mode, the chip receives 50mhz reference clock from an external oscillator or opposite rmii interface . ? provides independent 2 - bit wide (bi - bit) transmit and rece ive data paths. ksz8895rq supports mac5 rmii interfaces at the switch side : ? for t he detail of sw 5 - rmii (port 5 mac5 rmii ) signals connection see the t able below: ? t he ksz8895 rq can provide a 50mhz reference clock for both mac to mac and mac to phy rmii in terfaces when sw 5 - rmii is used in the clock mode of the device (default with strap pin led2_2 internal pull - up for the clock mode). ? t he ksz8895 rq can also receive a 50mhz reference clock from an external 50mhz clock source or opposite rmii to sw5 - rmii smtx c pin when the device is set to normal mode (the strap pin led2_2 is pulled down). when the device is strapped to normal mode by pin led2_2 pull - down , the reference clock come s from smtxc which will be used as the device ?s clock source . the external 25mhz crystal clock from pins x1/x2 will be ignored . not e: in normal mode, the 50mhz clock from smtxc will be used as the clock source for whole device. the phy5 pmtxc/pmrefclk pin cannot be used as the clock source for whole device . t he pin of pmtxc/pmrefclk can receive the 50mhz clock from pmrxc when the device is strap ped to normal mode and an external 50mhz reference clock comes in from pin smtxc. in normal mode, the 50mhz clock on pin smrxc can be disabled by register, and the pmrxc 50mhz clock can be used when p5 - rmii interface is used. there is a register 12 bit 6 to monitor the status of the device for the clock mode or normal mode. when us ing an external 50mhz clock source as rmii reference clock, the ksz8895rq should be set to normal mode by pull ing do wn its led2_2 strap - in pin first before power up reset or w a rm reset . t he normal mode of the ksz8895rq device will start to work when it get s the 50mhz reference clock from pin smtxc/smrefclk from an external 50mhz clock source. for the rmii connection exa mples, please refer to app not e in the desig n kit. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 39 r evision 1. 6 sw 5 - rmii mac to mac connection (?phy mode ? ) sw 5 - rmii mac to phy connection (?mac mode ? ) external mac ksz8895 rq sw5 - rmii ksz8895 rq sw signal type description external phy ksz8895 rq sw5 - rmii ksz8895 rq sw signal type ref_clk smrxc o utput (clock mode with 50mhz) (normal mode without connection) reference clock -------- smt xc / sm refclk i nput ( clock comes from smrx c in clock mode or external clock in normal mode ) c rs_dv smrxdv /smcrsdv o utput carier sens e/receive data valid crs_dv smtxen i nput rxd1 smrxd[1] o utput receive data bit 1 rxd1 smtxd[1] i nput rxd0 smrxd[0] o utput receive data bit 0 rxd0 smtxd[0] i nput tx_en smtxen i nput transmit data enable tx_en smrxdv /smcrsdv o utput txd1 smtxd[1] i nput tr ansmit data bit 1 txd1 smrxd[1] o utput txd0 smtxd[0] i nput transmit data bit 0 txd0 smrxd[0] o utput (not used) (not used) receive error (not used) (not used) --- smtxc / sm refclk i nput ( clock comes from smrxc in clock mode or external clock in normal mode ) reference clock ref_clk smrxc o utput (clock mode with 50mhz ) (normal mode without connection) not e: 1. mac/phy mode in rmii is difference with mac/phy mode in mii, there is no strap pin and register configuration request in rmii , just follow the signal s connection in the table. table 5 . port 5 mac5 sw5 - rmii connection micrel, inc. ksz8895mq/rq/fmq january 22, 2013 40 r evision 1. 6 sni interface operation the serial network interface (sni) is compatible with some controllers used for network layer protocol processing. this interface can b e directly connected to these types of devices. the signals are divided into two groups, one for transmission and the other for reception. the signals involved are described in table 6 . sni signal description ksz8895mq/rq/fmq signal txen transmit enable smtxen txd serial transmit data smtxd[0] txc transmit clock smtxc col collision detection scol crs carrier sense smrxdv rxd serial receive data smrxd[0] rxc receive clock smrxc table 6 . sni signals this interface is a bit - w ide data interface , so it runs at the network bit rate ( not encoded). an additional signal on the transmit side indicates when data is valid. likewise, the receive side has an indicator that shows when the data is valid. for half - duplex operation there is a signal that indicates a collision has occurred during transmission. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 41 r evision 1. 6 advanced functionality qos priority support the ksz8895mq/rq/fmq provides quality of service (qos) for applications such as voip and video conferencing. the ksz8895mq/rq/fmq offers on e, two, or four priority queues per port by setting the port registers xxx control 9 bit 1 and the port registers xxx control 0 bit 0, the 1/2/4 queues split as follows, [port registers xxx control 9 bit 1, control 0 bit 0] = 00 single output queue as defa ult. [port registers xxx control 9 bit 1, control 0 bit 0] = 01 egress port can be split into two priority transmit queues. [port registers xxx control 9 bit 1, control 0 bit 0] = 10 egress port can be split into four priority transmit queues. t he four pri ority transmit queue is a new feature in the ksz8895mq/rq/fmq . the queue 3 is the highest priority queue and q ueue 0 is the lowest priority queue. the port registers xxx control 9 bit 1 and the port registers xxx control 0 bit 0 are used to enable split tr ansmit queues for ports 1, 2, 3, 4 and 5, respectively. if a port's transmit queue is not split, high priority and low priority packets have equal priority in the transmit queue. there is an additional option to either always deliver high priority packets first or to use programmable weighted fair queuing for the four priority queue scale by the port registers control 1 0 , 1 1 , 1 2 and 13 (default value are 8, 4, 2, 1 by their bit[6:0]. register 130 bit[7:6] prio_2q[1:0] is used w hen the 2 queue configuratio n is selected, these bits are used to map the 2 - bit result of ieee 802.1p from the registers 128, 129 or tos/diffserv mapping from registers 144 - 159 (for 4 queues) into two - queue mode with priority high or low. please see the descriptions of the register 1 30 bits [7:6] for detail. port - based priority with port - based priority, each ingress port is individually classified as a priority 0 - 3 receiving port. all packets received at the priority 3 receiving port are marked as high priority and are sent to the hig h - priority transmit queue if the corresponding transmit queue is split . th e port registers control 0 bits [4:3] is used to enable port - based priority for ports 1, 2, 3, 4 and 5, respectively. 802.1p - based priority for 802.1p - based priority, the ksz8895mq/rq /fmq examines the ingress (incoming) packets to determine whether they are tagged. if tagged, the 3 - bit priority field in the vlan tag is retrieved and compared against the ?priority mapping? value, as specified by the registers 128 and 129 , both register 128/129 can map 3 - bit priority field of 0 - 7 value to 2 - bit result of 0 - 3 priority levels. the ?priority mapping? value is programmable. the following figure illustrates how the 802.1p priority field is embedded in the 802.1q vlan tag. figure 6 . 802.1p priority field format 802.1p - b ased priority is enabled by bit [5] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 42 r evision 1. 6 the ksz8895mq/rq/fmq provides the option to insert or remove the priority tagged frame's he ader at each individual egress port. this header, consisting of the two - byte v lan protocol id (vpid) and the two - byte tag control information field (tci), is also referred to as the ieee 802.1q vlan tag. tag insertion is enabled by bit [2] of the port regis ters control 0 and the port register control 8 to select which source port (ingress port) pvid can be inserted on the egress port for ports 1, 2, 3, 4 and 5, respectively. at the egress port, untagged packets are tagged with the ingress port?s default tag. the default tags are programmed in the port registers control 3 and control 4 for ports 1, 2, 3, 4 and 5, respectively. the ksz8895mq/rq/fmq will not add tags to already tagged packets. tag removal is enabled by bit [1] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively. at the egress port, tagged packe ts will have their 802.1q vlan t ags removed. the ksz8895mq/rq/fmq will not modify untagged packets. the crc is recalculated for both tag insertion and tag removal. 802.1p priority field re - mapping is a qos feature that allows the ksz8895mq/rq/fmq to set the ?user priority ceiling? at any ingress port by the port register control 2 bit 7. if the ingress packet?s priority field has a higher priori ty value than the default tag?s priority fie ld of the ingress port, the packet?s priority field is replaced with the default tag?s priority field. diffserv - based priority diffserv - based priority uses the tos registers (registers 144 to 159) in the advanced control registers section. the tos priorit y control registers implement a fully decoded, 128 - bit differentiated services code point (dscp) register to determine packet priority from the 6 - bit tos field in the ip header. when the most significant six bits of the tos field are fully decoded, 64 code points for dscp result. these are compared with the corresponding bits in the dscp register to determine priority. spanning tree support port 5 is the designated port for spanning tree support. the other ports (port 1 ? p ort 4) can be configured in one of t he five spanning tree states via ?transmit enable,? ?receive enable,? and ?learning disable? register settings in re gisters 18, 34, 50, and 66 for p orts 1, 2, 3, and 4, respectively. the following description shows the port setting and software actions tak en for each o f the five spanning tree states: disable state: the port should not forward or receive any packets. learning is disabled. port setting: "transmit enable = 0, receive enable = 0, learning disable = 1." software action: the processor should not send any packets to the port. the switch may still send specific packets to the processor (packets that match some entries in the static table with ?overriding bit? set) and the processor should discard those packets. not e: the processor is connected to p o rt 5 via mii interface. address learning is disabled on the port in this state. blocking state: only packets to the processor are forwarded. learning is disabled. p ort setting: "transmit enable = 0, receive enable = 0, learning disable = 1" software action : the processor should not send any packets to the port(s) in this state. the processor should program the ?static mac table? with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should also be set so that the switch will fo rward those specific packets to the processor. address learning is disabled on the port in this state. listening state: only packets to and from the processor are forwarded. learning is disabled. port setting: "transmit enable = 0, receive enable = 0, lear ning disable = 1. "software action: the processor should program the static mac table with the entries that it needs to receive (e.g. bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state, see ?tail tagging mode? section for details. address learning is disabled on the port in this state. learning state: only packets to and from the processor are forwarded. learning is enabled. po rt setting: ?transmit enable = 0, receive en able = 0, learning disable = 0.? micrel, inc. ksz8895mq/rq/fmq january 22, 2013 43 r evision 1. 6 software action: the processor should program the static mac table with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state, see ?tail tagging mode? section for details. address learning is enabled on the port in this state. forwarding state: packets are forw arded and received normally. learning is enabled. p ort setting: ?transmit enable = 1, receive enable = 1, learning disable = 0.? software action: the processor should program the static mac table with the entries that it needs to receive (e.g., bpdu packet s). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state, see ?tail tagging mode? section for details. address learning is enabled on the por t in this state. rapid spanning tree support there are three operational states of discarding, learning, and forwarding assigned to each port for rstp: discarding ports do not participate in the active topology and do not learn mac addresses. discarding state: the state includ e s three states of the disable, blocking and listening of stp. port setting: "transmit enable = 0, receive enable = 0, learning disable = 1." software action: the processor should not send any packets to the port. the switch may stil l send specific packets to the processor (packets that match some entries in the static table with ?overriding bit? set) and the processor should dis card those packets. when disabling the port?s learning capability (learning disable = ?1?), set the registe r 1 bit 5 and bi t 4 will flush rapidly with the port related entries in the dynamic mac table and static mac table. not e : the processor is connected to p ort 5 via mii interface. address learning is disabled on the port in this state. ports in learning sta tes learn mac addresses, but do not forward user traffic. learning state: only packets to and from the processor are forwarded. learning is enabled. port setting: ?transmit enable = 0, receive enable = 0, learning disable = 0.? software action: the proces sor should program the static mac table with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s ) in this state, see ?tail tagging mode? section for details. address learning is enabled on the port in this state. ports in forwarding states fully participate in both data forwarding and mac learning. forwarding state: packets are forwarded and received normally. learning is enabled. port setting: ?trans mit enable = 1, receive enable = 1, learning disable = 0.? software action: the processor should program the static mac table with the entries that it needs to receive (e.g., bpdu packets). the ?overridin g? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state, see ?tail tagging mode? section for details. address learning is enabled on the port in this state. r stp uses only one type of bpdu called rstp bpdus. they are similar to stp configuration bpdus with the exception of a type field set to ?version 2? for rstp and ?version 0? for stp, and a flag field carrying additional information. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 44 r evision 1. 6 tail tagging mode the t ail ta g is only seen and used by the p ort 5 interface, which should be connected to a processor by sw5 - mii interface. the one byte tail tagging is used to indicate the sou rce/destination port in p ort 5. only bit [3 ? 0] are used for the destination in the ta il tag ging byte. other bits are not used. the tail tag feature is enabled by setting register 12 bit 1 . figure 7 . tail tag frame format ingress to port 5 (host --> ksz8895mq/rq/fmq ) bit [3:0] destination 0,0,0,0 normal (addre ss look up for destination) 0,0,0,1 port 1 (direct forward to p ort1) 0,0,1,0 port 2 (direct forward to p ort2) 0,1,0,0 port 3 (direct forward to p ort3) 1,0,0,0 port 4 (direct forward to p ort4) 1,1,1,1 port 1 , 2,3 and 4 (direct forward to p ort 1,2,3,4,) bit [7:4] 0,0,0,0 queue 0 is used at destination port 0,0,0,1 queue 1 is used at destination port 0,0,1,0 queue 2 is used at destination port 0,0,1,1 queue 3 is used at destination port x, 1,x,x reserved 1, x,x,x bit[6:0] will be ignored as normal egress from port 5 ( ksz8895mq/rq/fmq -- > host) bit [1:0] source 0,0 port 1 (packets from p ort 1) 0,1 port 2 (packets from p ort 2) 1,0 port 3 (packets from p ort 3) 1,1 port 4 (packets from p ort 4) table 7 . tail tag rules micrel, inc. ksz8895mq/rq/fmq january 22, 2013 45 r evision 1. 6 ig mp support there are two parts involved to support the internet group managem ent protocol (igmp) in l ayer 2 . t he first part is igmp snooping, the second part is this igmp packet to be sent back to the subscribed port. describe them as follows. ? igmp snoopi ng the ksz8895mq/rq/fmq traps igmp packets and forwar ds them only to the processor (p ort 5 sw5 - mii /rmii ). the igmp packets are identified as ip packets (either ethernet ip packets, or ieee 802.3 snap ip packets) with ip version = 0x4 and protocol version number = 0x2. s et register 5 bit [6] to ?1? to enable igmp snooping. ? igmp send back to the subscri bed port once the host responds the received igmp packet , the host should know the original igmp ingress port and send back the igmp packet to this port only , otherwise this igmp packet will be broadcasted to all port to downgrade the performance. enable the tail tag mode, the host will know the igmp packet received port from tail tag bits [1:0] and can send back the response igmp packet to this subscribed p ort by setting the bits [3:0] in the t ail tag . enable ?tail tag mode? by setting register 12 bit 1 . port mirroring support the ksz8895mq/rq/fmq supports ?port mirror? comprehensively as: ? ?receive only? mirror on a port all the packets received on the port will be mirrored on the sniffer port. for example, p ort 1 is pr ogrammed to be ?rx sniff,? and p ort 5 is programmed to be the ?sniffer port.? a pa cket, received on port 1, is destined to p ort 4 after the internal look - up. the ksz8895mq/rq/fmq w ill forward t he packet to both port 4 and p ort 5. ksz8895mq/rq/fmq can optionally forward even ?bad? received packets to p ort 5. ? ?transmit only? mirror on a port all the packets transmitted on the port will be mirrored on the sniffer port. for example, p ort 1 is pr ogra mmed to be ?tx sniff,? and p ort 5 is programmed to be the ?sniffer port.? a packet, received on an y of the ports, is destined to p ort 1 after the internal look - up. the ksz8895mq/rq/fmq w ill forward the packet to both p orts 1 and 5. ? ?receive and transmit? m irror on two ports. all the packets received on port a and transmitted on port b will be mirrored on the sniffer port. to turn on the ?and? feature, set regis ter 5 bit 0 to 1. for example, p ort 1 i s programmed to be ?rx sniff,? p ort 2 is programm ed to be ?transmit sniff,? and p ort 5 is programmed to be the ?sniffe r port.? a packet, received on port 1, is destined to p ort 4 after the internal look - up. the ksz8895mq/rq/fmq will forward the packet to p ort 4 only, since it does not meet the ?and? co ndition. a packet, received on port 1, is destined to p ort 2 after the internal look - up. the ksz8895mq/rq/fmq will forward the packet to both port 2 and p ort 5. multiple ports can be selected to be ?rx sniffed? or ?tx sniffed.? and any port can be selected to be the ?sniffer port.? all these per port features can be selected through register 17. vlan support the ksz8895mq/rq/fmq supports 128 active vlans and 4096 possible vids specified in ieee 802.1q. ksz8895mq/rq/fmq provides a 128 - entry vlan table, which correspon d to 4096 possible vids and converts to fid (7 bits) for address look - up max 128 active vlans. if a non - tagged or null - vid - tagged packet is received, then the ingress port vid is used for look - up when 802.1q is enabled by the global register 5 control 3 bi t 7 . in the vlan mode, the look - up process starts from vlan table look - up to determine whether the vid is valid. if the vid is not valid, the packet will then be dropped and its address will not be learned. if the vid is valid, fid is retrieved for further look - up by the static mac table or dynamic mac table . fid+da is used to determine the destination port. t he follow ing table describes the differen t actions in different situ a tions of da and fid+da in the static mac table and dynamic mac table after the vl an table finish a look - up action. fid+sa is used for learning purposes. t he follow ing table also describ es learning in the dynamic mac table when the vlan table has done a look - up in the static mac table without a valid entry. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 46 r evision 1. 6 da found in static mac tabl e use fid flag? fid match? da+fid found in dynamic mac table action no do not care do not care no broadcast to the membership ports defined in the vlan table bit[11:7]. no do not care do not care yes send to the destination port defined in the dynamic mac table bit[57:55]. yes 0 do not care do not care send to the destination port(s) defined in the static mac table bit[52:48]. yes 1 no no broadcast to the membership ports defined in the vlan table bit[11:7]. yes 1 no yes send to the destination po rt defined in the dynamic mac table bit[57:55]. yes 1 yes do not care send to the destination port(s) defined in the static mac table bit[52:48]. table 8 . fid+da look - up in the vlan mode sa+fid found in dynamic mac table actio n no the sa+fid will be learned into the dynamic table. yes time stamp will be updated. table 9 . fid+sa look - up in the vlan mode advanced vlan features are also supported in ksz8895mq/rq/fmq , such as ?vlan ingress filtering? a nd ?discard non pvid? defined in bits [6:5] of the port register control 2. these features can be controlled on a port basis. rate limiting support the ksz8895mq/rq/fmq provides a fine resolution hardware rate limiting . the rate step is 64kbps when the rat e limit is less than 1mbps rate for 100bt or 10bt. the rate step is 1mbps when the rate limit is more than 1mbps rate for 100bt or 10bt (refer to data rate selection table which follow the end of the port register queue 0 ? 3 ingress/egress limit control sec tion). the rate limit is independently on the ?receive side? and on the ?transmit side? on a per port basis. for 10base - t, a rate setting above 10 mbps means the rate is not limited. on the receive side, the data receive rate for each priority at each port can be limited by setting up ingress rate control registers. on the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up egress rate control registers. the size of each frame has options to include minimu m ifg (inter frame gap) or preamble byte, in addition to the data field (from packet da to fcs). ingress rate limit for ingress rate limiting, ksz8895mq/rq/fmq provides options to selectively choose frames from all types, multicast, broadcast, and flooded unicast frames by bits [3 ? 2] of the port rate limit control register. the ksz8895mq/rq/fmq counts the data rate from those selected type of frames. packets are dropped at the ingress port when the data rate exceeds the specified rate limit or the flow con trol takes effect without packet dropped when the ingress rate limit flow control is enabled by the port rate limit control register bit 4. the ingress rate limiting supports the port - based , 802.1p and diffserv - based priorit ies, the port - based priority is fixed priority 0 ? 3 selection by bits [4 - 3] of the port register control 0. the 802.1p and diffserv - based priority can be mapped to priority 0 ? 3 by default of the register 128 and 129. in the ingress rate limit, set register 135 global control 19 bit 3 to en able queue - based rate limit if us ing two - queue or four - queue mode . a ll related ingress ports and egress port should be sp lit to two - queue or four - queue mode by the port registers co ntrol 9 and control 0. the four - queue mode will use q0 ? q3 for priority 0 ? 3 by bit [6 ? 0] of the port register ingress limit control 1 ? 4 . the two - queue mode will use q0 ? q1 for priority 0 - 1 by bit [6 - 0] of the port register ingress limit control 1 ? 2 . the priority level s in the packets of the 802.1p and diffserv can be program med to pri ority 0 ? 3 by the register 128 and 129 for a re - mapping. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 47 r evision 1. 6 egress rate limit for egress rate limiting, the leaky bucket algorithm is applied to each output priority queue fo r shaping output traffic. inter frame gap is stretched on a per frame base to generate smooth, non - burst egress traffic. the throughput of each output priority queue is limited by the egress rate specified by the data rate selection table followed the egress rate limit control registers. if any egress queue receives more traffic than the spe cified egress rate throughput, packets may be accumulated in the output queue and packet memory. after the memory of the queue or the port is used up, packet dropping or flow control will be triggered. as a result of congestion, the actual egress rate may be dominated by flow control/dropping at the ingress end, and may be therefore slightly less than the specified egress rate. the egress rate limiting supports the port - based , 802.1p and diffserv - based priorit ies, the port - based priority is fixed priority 0 ? 3 selection by bits [4 ? 3] of the port register control 0. the 802.1p and diffserv - based priority can be mapped to priority 0 ? 3 by default of the register 128 and 129. in the e gress rate limit, set register 135 global control 19 bit 3 for queue - based rate l imit to be enabled if us ing two - queue or four - queue mode . a ll related ingress ports a nd egress port should be split to two - queue or four - queue mode by the port registers co ntrol 9 and control 0. the four - queue mode will use q0 - q3 for priority 0 ? 3 by bit [6 - 0] of the port register egress limit control 1 ? 4 . the two - queue mode will use q0 - q1 for priority 0 ? 1 by bit [6 ? 0] of the port register egress limit control 1 ? 2 . the priority level s in the packets of the 802.1p and diffserv can be program med to priority 0 ? 3 b y the register 128 and 129 for a re - mapping. when the egress rate is limit ed , just use one queue per port for the egress port rate limit . t he priority packets will be based up on the data rate selection table (see tables 13 and 14) . if the egress rate limit use s more than one queue per port for the egress port rate limit, then the highest priority packets will be based up on the data rate selection table for the rate limit exact number . o ther lower priority packet rate s will be limited based up on 8:4:2:1 (def ault) priority ratio , which is based on the highest priority rate. the transmit queue priority ratio is programmable. to reduce congestion, it is good practice to make sure the egress bandwidth exceeds the ingress bandwidth. transmit queue ratio programmin g in transmit queues 0 ? 3 of the egress port, the default priority ratio is 8:4:2:1 . t he priority ratio can be programmed by the port registers control 10, 11, 12 and 13. when the transmit rate exceed s the ratio limit in the transmit queue, the transmit rat e will be limited by the transmit queue 0 ? 3 ratio of the port register control 10, 11, 12 and 13. the highest priority queue will not be limited . o ther lower priority queues will be limited based on the transmit queue ratio. filtering for self - address, unk nown unicast/ m ulticast a ddress and u nknown vid p acket/ip m ulticast enable self - address filtering , the unknown unicast packet filtering and forwarding by the r egister 131 global c ontrol 1 5 . enable unknown multicast packet filtering and forwarding by the r eg ister 132 global c ontrol 16 . enable unknown vid packet filtering and forwarding by the r egister 133 global c ontrol 17 . enable unknown ip multicast packet filtering and forwarding by the r egister 134 global c ontrol 18 . this function is very useful in preven ting packets that could degrade the quality of the port in applications such as voice over internet protocol (voip) and the daisy chain connection . configuration interface i 2 c master serial bus configuration if a 2 - wire eeprom exists, then the ksz8895mq/rq /fmq can perform more advanced features like broadcast storm protection and rate control. the eeprom should have the entire valid configuration data from register 0 to register 255 defined in the ?memory map,? except the chipid = 0 in the register1 and the status registers. after reset, the ksz8895mq/rq/fmq will start to read all 255 registers sequentially from the eeprom. the configuration access time (t prgm ) is less than 30ms , as shown in figure 8 . micrel, inc. ksz8895mq/rq/fmq january 22, 2013 48 r evision 1. 6 figure 8 . ksz8895mq/rq/fmq eeprom c onfiguration timing diagram to configure the ksz8895mq/rq/fmq with a pre - configured eeprom use the following steps: 1. at the board level, connect pin 110 on the ksz8895mq/rq/fmq to the s cl pin on the eeprom. connect pin 111 on the ksz8895mq/rq/fmq to the sda pin on the eeprom. 2. a[2 - 0] address pins of eeprom should be tied to ground for address a[2 - 0] = ? 000 ? to be identified by the ksz8895mq/rq/fmq . 3 . set the input signals ps[1:0] (pi ns 113 and 114, respectively) to ?00.? this puts the ksz8895mq/rq/fmq serial bus configuration into i 2 c master mode. 4 . be sure the board - level reset signal is connected to the ksz8895mq/rq/fmq reset signal on pin 115 (rst_n). 5 . program the contents of th e eeprom before placing it on the board with the desired configuration data. not e that the first byte in the eeprom must be ?95? for the loading to occur properly. if this value is not correct, all other data will be ignored. 6 . place eeprom on the board a nd power up the board. assert the active - low board level reset to rst_n on the ksz8895mq/rq/fmq . after the reset is de - asserted, the ksz8895mq/rq/fmq will begin reading configuration data from the eeprom. the configuration access time (t prgm ) is less than 30ms. not e: for proper operation, make sure that pin 47 (pwrdn_n) is not asserted during the reset operation. spi slave serial bus configuration the ksz8895mq/rq/fmq can also act as a spi slave device. through the spi, the entire feature set can be enable d, including ?vlan,? ?igmp snooping,? ?mib counters,? etc. the external master device can access any register from register 0 to register 127 randomly. the system should configure all the desired settings before enabling the switch in the ksz8895mq/rq/fmq . to enable the switch, write a "1" to register 1 bit 0. two standard spi commands are supported (00000011 for ?read data,? and 00000010 for ?write data?). to speed configuration time, the ksz8895mq/rq/fmq also supports multiple reads or writes. after a byt e is written to or read from the ksz8895mq/rq/fmq , the internal address counter automatically increments if the spi slave select signal (spis_n) continues to be driven low. if spis_n is kept low after the first byte is read, the next byte at the next addre ss will be shifted out on spiq. if spis_n is kept low after the first byte is written, bits on the master out slave input (spid) line will be written to the next address. asserting spis_n high terminates a read or write operation. this means that the spis_ n signal must be asserted high and then low again before issuing a not her command and address. the address counter wraps back to zero once it reaches the highest address. therefore the entire register set can be written to or read from by issuing a single c ommand and address. the default spi clock speed is 12.5mhz. the ksz8895mq/rq/fmq is able to support a spi bus up to 25 mhz (set register 12 bit [5:4] = 0x10) . a high performance spi master is recommended to prevent internal counter overflow. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 49 r evision 1. 6 to use the ksz 8895mq/rq/fmq spi: 1. at the board level, connect ksz8895mq/rq/fmq pins as follows: ksz8895mq/rq/fmq pin number ksz8895mq/rq/fmq signal name microprocessor signal description 112 spis_n spi slave select 110 spic spi clock 111 spid master out slave i nput 109 spiq master in slave output table 10. spi connections 2. set the input signals ps[1:0] (pins 113 and 114, respectively) to ?10? to set the serial configuration to spi slave mode. 3. power up the board and assert a rese t signal. after reset wait 100s, the start switch bit in register 1 will be set to ?0?. configure the desired settings in the ksz8895mq/rq/fmq before setting the start register to ?1.' 4. write configuration to registers using a typical spi write data cyc le as shown in figure 9 or spi multiple write as shown in figure 11. not e that data input on spid is registered on the rising edge of spic. 5. registers can be read and configuration can be verified with a typical spi read data cycle as shown in figure 10 or a multiple read as shown in figure 12. not e that read data is registered out of spiq on the falling edge of spic. 6. after configuration is written and verified, write a ?1? to register 1 bit 0 to begin ksz8895mq/rq/fmq switch operation. spiq spic spid spis_n 0 0 0 0 0 0 1 0 x a7 a6 a5 a4 a3 a2 a1 a0 write command write address write d at a d2 d0 d1 d3 d4 d5 d6 d7 figure 9 . spi write data cycle spiq spic spid spis_n 0 0 0 0 0 0 1 1 x a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 read command read address read d at a figure 10 . spi read data cycle micrel, inc. ksz8895mq/rq/fmq january 22, 2013 50 r evision 1. 6 spiq spic spid spis_n 0 0 0 0 0 0 1 0 x a7 a6 a5 a4 a3 a2 a1 a0 write command write address byte 1 d2 d0 d1 d3 d4 d5 d6 d7 spiq spic spid spis_n d7 d6 d5 d4 d4 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 byte 2 byte 3 ... byte n d2 d0 d1 d3 d4 d5 d6 d7 figure 11 . spi multiple write spiq spic spid spis_n 0 0 0 0 0 0 1 1 x a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 read command read address byte 1 x x x x x x x x x x x x x x x x byte 2 byte 3 ... byte n x x x x x x x x x x x x x x x x d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 spiq spic spid spis_n figure 12 . spi multiple read micrel, inc. ksz8895mq/rq/fmq january 22, 2013 51 r evision 1. 6 mii management interface ( miim) the ksz8895mq/rq/fmq supports the standard ieee 802.3 mii management interface, also known as the management data input/output (mdio) interface. this interface allows upper - layer devices to monitor and control the states of the ksz8895mq/rq/fmq . an e xternal device with mdc/mdio capability is used to read the phy status or configure the phy settings. further detail s on the miim interface are found in clause 22.2.4.5 of the ieee 802.3u specification. the miim interface consists of the following: ? a physi cal connection that incorporates the data line ( pin 108 mdio) and the clock line ( pin 107 mdc). ? a specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the ksz8895mq/rq/fmq devi ce. ? access to a set of eight 16 - bit registers, consisting of 8 standard miim registers [0:5h], 1d and 1f miim registers per port. the miim interface can operate up to a maximum clock speed of 10 mhz mdc clock. table 11 depicts the mii management interface frame format. preamble start of frame read/write op code phy address bits[4:0] reg address bits[4:0] ta data bits[15:0] idle read 32 1?s 01 10 aaaaa rrrrr z0 dddddddd_dddddddd z write 32 1?s 01 01 aaaaa rrrrr 10 dddddddd_dddddddd z table 11. mii management interface frame format the miim interface does not have access to all the configuration registers in the ksz8895mq/rq/fmq . it can only access the standard miim registers. see ?miim registers?. the spi interface and mdc/mdio sm i mode, on the other hand, can be used to access all registers with the entire ksz8895mq/rq/fmq feature set. serial management interface (smi) the smi is the ksz8895mq/rq/fmq non- standard miim interface that provides access to all ksz8895mq/rq/fmq configur ation registers. this interface allows an external device with mdc/mdio interface to completely monitor and control the states of the ksz8895mq/rq/fmq . the smi interface consists of the following: ? a physical connection that incorporates the data line (mdio ) and the clock line (mdc). ? a specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the ksz8895mq/rq/fmq device. ? access to all ksz8895mq/rq/fmq configuration registers. register access includes the global, port and advanced control registers 0 - 255 (0x00 ? 0xff), and indirect access to the standard miim registers [0:5] and custom miim registers [29, 31]. the smi interface can operate up to a maximum clock speed of 1 0 mhz mdc clock . table 12 depicts the smi frame format. preamble start of frame read/write op code phy address bits[4:0] reg address bits[4:0] ta data bits [15:0] idle read 32 1?s 01 10 rr11r rrrrr z0 0000_0000_dddd_dddd z write 32 1?s 01 01 rr11r rrrrr 10 xxxx_xxxx_dd dd_dddd z table 12. serial management interface (smi) frame format micrel, inc. ksz8895mq/rq/fmq january 22, 2013 52 r evision 1. 6 smi register read access is selected when op code is set to ?10? and bit s [2:1] of the phy address is set to ?11?. the 8 - bit register address is the concatenati on of {phy address bit s [4:3], phy address bit s [0], reg address bit [4:0]}. ta is turn - around bits. ta bits [1:0] are ?z0? means the processor mdio pin is changed to input hi - z from output mode and the followed ?0? is the read response from device , as the switch configuration registers are 8 - bit wide, only the lower 8 bits of data bits [15:0] are used smi register write access is selected when op code is set to ? 01 ? and bit s [2:1] of the phy address is set to ?11?. the 8 - bit register address is the conc atenation of {phy address bit s [4:3], phy address bit s [0], reg address bit [4:0]}. ta bits [1:0] are set to ? 1 0? , as the switch configuration registers are 8 - bit wide, only the lower 8 bits of data bits [15:0] are used . to access the ksz8895mq/rq/fmq regi sters 0 - 255 (0x00 - 0xff), the following applies: phyad [4, 3, 0] and regad [4:0] are concatenated to form the 8 - bit address; that is, {phyad [ 4, 3, 0], regad [4:0]} = bits [7:0] of the 8 - bit address. registers are 8 data bits wide. for read operation, dat a bits [15:8] are read back as zeroes . for write operation, data bits [15:8] are not defined, a nd hence can be set to either zeroes or ones. smi register access is the same as the miim register access, except for the register access requirements presented in this section. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 53 r evision 1. 6 register description offset decimal hex description 0 ? 1 0x00 - 0x01 chip id registers. 2 ? 13 0x02 - 0x0d global control registers . 14? 15 0x0e - 0x0f power down management control registers . 16? 20 0x10 - 0x14 p ort 1 control regis ters. 21? 23 0x15 - 0x17 port 1 reserved (factory test registers) . 2 5 ? 31 0x18 - 0x1f port 1 control/status registers . 32? 36 0x20 - 0x24 port 2 control registers . 37? 39 0x25 - 0x27 port 2 reserved (factory test registers) . 40? 47 0x28 - 0x2f port 2 control /status registers . 48? 52 0x30 - 0x34 port 3 control registers . 53? 55 0x35 - 0x37 port 3 reserved (factory test registers) . 56? 63 0x38 - 0x3f port 3 control/status registers. 64? 68 0x40 - 0x44 port 4 control registers. 69? 71 0x45 - 0x47 port 4 reserved (fa ctory test registers) . 72? 79 0x48 - 0x4f port 4 control/status registers. 80? 84 0x50 - 0x54 port 5 control registers. 85? 87 0x55 - 0x57 port 5 reserved (factory test registers) . 88? 95 0x58 - 0x5f port 5 control/sta tus registers. 96? 103 0x60 - 0x67 reser ved (factory testing registers) . 104? 109 0x68 - 0x6d mac address registers. 110? 111 0x6e - 0x6f in direct access control registers. 112? 120 0x70 - 0x78 indirect data registers. 121? 123 0x79 - 0x7b reserved (factory testing registers) . 124? 125 0x7c - 0x7d p ort interrupt registers . 126? 127 0x7e - 0x7f reserved (factory testing registers) . 128? 135 0x80 - 0x87 global control registers. 136 0x88 switch self test control register . 137? 143 0x89 - 0x8f qm global control registers . 144? 145 0x90 - 0x91 tos priority cont rol registers . 146? 159 0x92 - 0x9f tos priority control registers . 160? 175 0xa0 - 0xaf reserved (factory testing re gisters) . 176? 190 0xb0 - 0xbe port 1 control registers. 191 0xbf reserved (factory testing register): transmit queue remap base register . micrel, inc. ksz8895mq/rq/fmq january 22, 2013 54 r evision 1. 6 register description (continued) offset decimal hex description 192? 206 0xc0 - 0xce port 2 control registers. 207 0xcf reserved (factory testing register) . 208? 222 0xd0 - 0xde port 3 control registers. 223 0xdf reserved (factory testing re gister) . 224? 238 0xe0 - 0xee port 4 control registers . 239 0xef reserved (factory testing register) . 240? 254 0xf0 - 0xfe port 5 control registers . 255 0xff reserved (factory testing register) . micrel, inc. ksz8895mq/rq/fmq january 22, 2013 55 r evision 1. 6 global registers address name description mode defaul t register 0 (0x00): chip id0 7 ? 0 f amily id chip family. ro 0x95 register 1 (0x01): chip id1 / start switch 7 ? 4 chip id 0 1 00 = ksz8895mq 0110 = ksz8995rq 1100 = ksz8895fmq ro 0x 4 is mq 0x6 is rq 0xc is fmq 3 ? 1 revision id revision id ro 0x0 0 start switch 1, start the chip when external pins (ps1, ps0) = (1,0) not e: in (ps1,ps0) = (0,0) mode, the chip will start automatically, after trying to read the external eeprom. if eeprom does not exist, the chip will use default values f or all internal registers. if eeprom is present, the contents in the eeprom will be checked. the switch will check: 7 register 0 = 0x95, (2) register 1 [7:4] = availible chip id . if this check is ok, the contents in the eeprom will override chip registe r default values =0, chip will not start when external pins (ps1, ps0) = (1,0) or (0,1). not e: (ps1, ps0) = (1,1) for factory test only. 0, stop the switch function of the chip . r / w 0 register 2 (0x02): global control 0 7 new back - off enable new ba ck - off algorithm designed for unh 1 = enable 0 = disable r/w 0 6 reserved reserved. ro 0 5 flush dynamic mac table flush the entire dynamic mac table for rstp 1 = trigger the flush dynamic mac table operation. this bit is self clear 0 = normal operati on not e: all the entries associated with a port that has its learning capability being turned off (learning disable) will be flushed. if you want to flush the entire table, all ports learning capability must be turned off . r/w (sc) 0 4 flush static mac t able flush the matched ent r i es in static mac table for rstp 1 = trigger the flush static mac table operation. this bit is self clear 0 = normal operation not e: the ma t ched entry is defined as the entry whose forwarding ports field contains a single port a nd mac address with unicast. this port, in turn, has its learning capability being turned off (learning disable). per port, multiple entries can be qualified as matched entries. r/w (sc) 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 56 r evision 1. 6 global registers (continued) address name description mode de fault 3 enable phy mii /rmii 1, enable phy p5 - mii/rmii interface (default) . not e: if not enabled, the switch will tri - state all outputs. r/w 1 pin led[5][1] strap option. pd (0): isolate. pu (1): enable. not e: led[5][1] has internal pull - up (pu) . 2 reserved n/a do not change . r o 1 1 unh mode 1, the switch will drop packets with 0x8808 in t/l filed, or da = 01- 80-c2 -00 -00- 01. 0, the switch will drop packets qualified as ?flow control? packets. r/w 0 0 link change age 1, link change from ?li nk? to ?no link? will cause fast aging (<800s) to age address table faster. after an age cycle is complete, the age logic will return to normal (300 + / - 75 seconds ). not e: if any port is unplugged, all addresses will be automatically aged out. r/w 0 register 3 (0x03): global control 1 7 pass all frames 1, switch all packets including bad ones. used solely for debugging purpose. works in conjunction with sniffer mode. r/w 0 6 2k byte packet support 1 = enable support 2k byte packet 0 = disable s upport 2k byte packet r/w 0 5 ieee 802.3x transmit flow control disable 0, will enable transmit flow control based on an result. 1, will not enable transmit flow control regardless of an result. r/w 0 pin pmrxd3 strap option. pd (0): enable tx flo w control (default) . pu (1): disable tx/rx flow control. not e: pmrxd3 has internal pull - down. 4 ieee 802.3x receive flow control disable 0, will enable receive flow control based on an result. 1, will not enable receive flow control regardless of an result. not e: bit 5 and bit 4 default values are controlled by the same pin, but they can be programmed independently. r/w 0 pin pmrxd3 strap option. pd (0): enable rx flow control (default). pu(1): disable tx/rx flow control. not e: pmrxd3 has internal pull - down. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 57 r evision 1. 6 global registers (continued) address name description mode default 3 frame length field check 1, will check frame length field in the ieee packets if the actual length does not match, the packet will be dropped (for l/t <1500) . r/w 0 2 aging enable 1, enable age function in the chip. 0, disable aging function. r/w 1 pin led[5][2] strap option. pd (0): aging disable . p u(1): aging enable (default). not e: led[5][2] has internal pull up. 1 f ast age enable 1 = tu rn on fast age (800s). r/w 0 0 aggressive back off enable 1 = enable more aggressive back - off algorithm in half duplex mode to enhance performance. this is not an ieee standard. r/w 0 pin pmrxd0 strap option. pd (0 ): disable aggressive back off (de fault). pu (1): aggressive back off. not e: pmrxd0 has internal pull down. register 4 (0x04): global control 2 7 unicast port - vlan mismatch discard this feature is used for port vlan (described in register 17, register 33...). 1, all packets can not cross vlan boundary. 0, unicast packets (excluding unknown/ multicast/broadcast) can cross vlan boundary. r/w 1 6 multicast storm protection disable 1, ?broadcast storm protection? does not include multicast packets. only da = ffffffffffff packets wi ll be regulated. 0, ?broadcast storm protection? includes da = fff fffffffff and da[40] = 1 packet . r/w 1 5 back pressure mode 1, carrier sense based backpressure is selected. 0, collision based backpressure is selected. r/w 1 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 58 r evision 1. 6 global registers (con tinued) address name description mode default 4 flow control and back pressure fair mode 1, fair mode is selected. in this mode, if a flow control port and a non - flow control port talk to the same destination port, then packets from the non - flow co ntrol port may be dropped. this is to prevent the flow control port from being flow controlled for an extended period of time. 0, in this mode, if a flow control port and a non - flow control port talk to the same destination port, the flow control port will be flow controlled. this may not be ?fair? to the flow control port. r/w 1 3 no excessive c ollision drop 1, the switch will not drop packets when 16 or more collisions occur. 0, the switch will drop packets when 16 or more collisions occur. r/w 0 pin pmrxd1 strap option. pd (0): (default ) d rop excessive collision packets. pu(1): do not drop excessive collision packets. not e: pmrxd1 has internal pull down. 2 huge packet support 1, will accept packet sizes up to 1916 bytes (inclusive). this bit setting will override setting from bit 1 of the same register. 0, the max packet size will be determined by bit 1 of this register. r/w 0 1 legal maximum packet size check disable 1, will accept packet sizes up to 1536 bytes (inclusive). 0, 1522 bytes for ta gged packets ( not including packets with stpid from cpu to ports 1 - 4), 1518 bytes for untagged packets. any packets larger than the specified value will be dropped. r/w 0 pin pmrxer strap option. pd (0): (default) 1518/1522 byte packets. pu (1): 1536 byte p ackets. not e: pmrxer has internal pull - down. 0 reserved n/a r o 0 register 5 (0x05): global control 3 7 802.1q vlan enable 1, 802.1q vlan mode is turned on. vlan table needs to set up before the operation. 0, 802.1q vlan is disabled. r/w 0 6 igmp snoop enable on switch sw5 - mii/rmii interface 1, igmp snoop enabled. all the igmp packets will be forwarded to switch mii/rmii port. 0, igmp snoop disabled. r/w 0 5 enable direct mode on switch sw5 - mii/rmii interface 1, direct mode on p ort 5. this is a special mode for the switch mii/rmii interface. using preamble before mrxdv to direct switch to forward packets, bypassing internal look - up. 0, normal operation. r/w 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 59 r evision 1. 6 global registers (continued) address name description mode default 4 enable pre - tag on switch sw5 - mii/tmi /rmii i interface 1, packets forwarded to switch mii/rmii interface will be pre - tagged with the source port number (preamble before mrxdv). 0, normal operation. r/w 0 3 ? 2 reserved n/a r o 00 1 enable ?tag? mask 1, the last 5 digits in the vid field are used as a mask to determine which port(s) the packet should be forwarded to. 0, no tag masks. not e: you need to turn off the 802.1q vlan mode (reg0x5, bit 7 = 0) for this bit to work r/w 0 0 sniff mode select 1, wil l do rx and tx sniff (both source port and destination port need to match). 0, will do rx or tx sniff (either source port or destination port needs to match). this is the mode used to implement rx only sniff. r/w 0 register 6 (0x07): global control 4 7 switch sw5 - mii/rmii back p ressure enable 1, enable half - duplex back pressure on switch mii/rmii interface. 0, disable back pressure on switch mii interface. r/w 0 6 switch sw5 - mii/rmii half - duplex mode 1, enable mii/rmii interface half - duplex mode . 0, enable mii/rmii interface full - duplex mode. r/w 0 pin smrxd2 strap option. pd (0): (default) full - duplex mo de. pu (1): half - duplex mode. not e: smrxd2 has internal pull - down. 5 switch sw5 - mii/rmii flow control enable 1, enable full -du plex flow con trol on switch mii/rmii interface. 0, disable full - duplex flow control on switch mii/rmii interface. r/w 0 pin smrxd3 strap option. pd (0): (default) d isable flow control. pu (1): enable flow control. not e: smrxd3 has internal pull - down. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 60 r evision 1. 6 global regist ers (continued) address name description mode default 4 switch sw5 - mii/rmii speed 1, the switch sw5 - mii/rmii is in 10mbps mode. 0, the switch sw5 - mii /rmii is in 100mbps mode . r/w 0 pin smrxd1 strap option. pd (0): (default) enable 100mbps. pu (1): enabl e 10 mbps . not e: smrxd1 has internal pull - down. 3 null vid replacement 1, will replace null vid with port vid (12 bits). 0, no replacement for null vid. r/w 0 2 ? 0 broadcast storm protection rate bit[10:8] this along with the next register determine s how many ?64 byte blocks? of packet data allowed on an input port in a preset period. the period is 50ms for 100bt or 500ms for 10bt. the default is 1%. r/w 000 register 7 (0x07): global control 5 7 ? 0 broadcast storm protection rate bit[7:0] this along with the previous register determines how many ?64 - byte blocks? of packet data are allowed on an input port in a preset period. the period is 50ms for 100bt or 500ms for 10bt. the default is 1%. r/w 0x4a (1) register 8 (0x08): global control 6 7 ? 0 factory testing n/a do not change . r o 0x 00 register 9 (0x09): global control 7 7 ? 0 factory testing n/a do not change . r o 0x 4c not e: 148,800 frames/sec 50ms/interval 1% = 74 frames/interval (approx.) = 0x4a. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 61 r evision 1. 6 global registers (continued) address name description mode default register 10 (0x0a): global control 8 7 ? 0 factory testing n/a do not change . r o 0x 00 register 11 (0x0b): global control 9 7 reversed n/a do not change . r o 0 6 port 5 sw5 - rmii reference clock edge select rq: select the data sampling edge of switch mac5 sw5 - rmii reference clock: 1 = data sampling on negative edge of refclk 0 = data sampling on positive edge of refclk (default) not e: mq/fmq is reserved with read only for this bit. r/w 0 5 reserved n/a do not change . r o 0 4 reserved n/a do not change . r o 0 3 phy power save 1 = disable phy power save mode. 0 = enable phy power save mode. r/w 0 2 reserved n/a do not change . r o 0 1 led mode 0 = led mode 0. 1 = led mode 1. mode 0, link at 100/full ledx[2,1,0] = 0,0,0 1 00/half ledx[2,1,0] = 0,1,0 10/full ledx[2,1,0] = 0,0,1 10/half ledx[2,1,0] = 0,1,1 mode 1, link at 100/full ledx[2,1,0] = 0,1,0 100/half ledx[2,1,0] = 0,1,1 10/full ledx[2,1,0] = 1,0,0 10/half ledx[2,1,0] = 1,0,1 (0 = led on, 1 = led off) r/w 0 pin smrxd0 ? strap option. pull - down(0): enabled led mode 0. pull - up(1): enabled led mode 1. not e: smrxd0 has internal pull - down 0. mode 0 mode 1 ledx_2 lnk/act 100lnk/act ledx_1 fulld/col 10lnk/act ledx_0 speed fulld 0 spi /smi read sampling clock edge select select the spi /smi clock edge for sampling spi /smi read data . 1 = trigger by rising edge of spi /smi clock ( for high speed spi about 25mhz and smi about 10mhz ) 0 = trigger by falling edge of spi /smi clock . r/w 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 62 r evision 1. 6 global regis ters (continued) address name description mode default register 12 (0x0c): global control 10 7 reserved reserved r o 0 6 s atus of device with rmii interface at clock mode or normal mode, default is clock mode with 25mhz crystal clock from pins x1/x2 (used for r mii of the ksz8895rq only ) 1 = the device is in clock mode when use rmii interface, 25 mhz crystal clock input as clock source for internal pll. this internal pll will provide the 50 mhz output on the pin smrxc for rmii reference clock (default) . 0 = the device is in normal mode when use sw4 - rmii interface and 50 mhz clock input from external clock through pin sm 4 txc as device?s clock source and internal pll clock source from this pin not from the 25mhz crystal. not e: this bit is set by strap o ption only. write to this bit has no effect on mode sel e ction . not e: the normal mode is used in sw 5 - rmii interface reference clock from external . ro 1 pin led[2][2] strap option. pd (0): s elect sw5 - rmii at normal mode to receive external 50mhz rmii refere nce clock pu (1): (default) select sw5 - rmii at clock mode, rmii output 50mhz not e: led[2][2] has internal pull - up. 5 ? 4 cpu interface clock select select the internal clock speed for spi, mdi interface: 00 = 41.67mhz (spi up to 6.25mhz, mdc up to 6mhz) 01 = 83.33mhz default (spi scl up to 12.5mhz, mdc up to 12mhz) 10 = 125mhz (for hign speed spi about 25mhz) 11 = reserved r/w 01 3 reserved n/a do not change . ro 0 2 enable restore preamble this bit is to enable phy5, when in 10bt mode, to restore preamble before sending data on p5 - mii interface. 1 = enable phy5 to restore preamble . 0 = disable phy5 to restore preamble . r/w 1 1 tail tag enable tail tag feature is applied for port 5 only. 1 = insert 1 byte of data right before fcs . 0 = do not insert . r/w 0 0 pass flow control packet 1 = switch will not filter 802.1x ?flow control? packets . 0 = switch will filter 802.1x ?flow control? packets . r/w 0 register 13 (0x0d): global control 11 7 ? 0 factory testing n/a do not change . ro 00000000 register 14 (0x0 e): power down management control 1 7 reserved n/a do not change . ro 0 6 reserved n/a do not change . ro 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 63 r evision 1. 6 global registers (continued) address name description mode default 5 pll power down pll power down enable: 1 = enable 0 = disable r/w 0 4 ? 3 pow er management mode power management mode : 00 = normal mode (d0) 01 = energy detection mode (d2) 10 = soft power down mode (d3) 11 = power saving mode (d1) r/w 00 pin led[ 4 ][ 0 ] strap option. pd (0): s elect energy detection mode pu (1): (default) normal mod e not e: led[ 4 ][0 ] has internal pull - up. 2 ? 0 reserved n/a do not change . ro 0 00 register 15 (0x0f): power down management control 2 7 ? 0 go_sleep_time[7:0] when the energy detect mode is on, this value is used to control the minimum period that the no ene rgy event has to be detected consecutively before the device enters the low power state. the unit is 20 ms. the default of go_sleep time is 1.6 seconds (80dec x 20ms) . r/w 01010000 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 64 r evision 1. 6 port registers the following registers are used to enable features that are assigned on a per port basis. the register bit assignments are the same for all ports, but the address for each port is different, as indicated. register 16 (0x10): port 1 control 0 register 32 (0x20): port 2 control 0 register 48 (0x30): port 3 contr ol 0 register 64 (0x40): port 4 control 0 register 80 (0x50): port 5 control 0 address name description mode default 7 broadcast storm protection enable 1, enable broadcast storm protection for ingress packets on the port. 0, disable broadcast sto rm protection. r/w 0 6 diffserv priority classification enable 1, enable diffserv priority classification for ingress packets on port. 0, disable diffserv function. r/w 0 5 802.1p priority classification enable 1, enable 802.1p priority classifica tion for ingress packets on port. 0, disable 802.1p. r/w 0 4 ? 3 port - based priority classification enable = 00, ingress packets on port will be classified as priority 0 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. = 01, ingress packets on port will be classified as priority 1 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. = 10, ingress packets on port will be classified as priority 2 queue if ?diffserv? or ?802.1p? classificatio n is not enabled or fails to classify. = 11, ingress packets on port will be classified as priority 3 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. not e: ?diffserv?, ?802.1p? and port priority can be enabled at the sa me time. the or?ed result of 802.1p and dscp overwrites the port priority. r/w 00 2 tag insertion 1, when packets are output on the port, the switch will add 802.1q tags to packets without 802.1q tags when received. the switch will not add tags to pack ets already tagged. the tag inserted is the ingress port?s ?port vid.? 0, disable tag insertion. r/w 0 1 tag removal 1, when packets are output on the port, the switch will remove 802.1q tags from packets with 802.1q tags when received. the switch wil l not modify packets received without tags. 0, disable tag removal. r/w 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 65 r evision 1. 6 port registers (continued) address name description mode default 0 two queue s split enable this bit 0 in the register16 /32/48/64/80 should be in combination with register177/ 193/209/225/241 bit 1 for p ort 1 -5 will select the split of ? /4 queues: for p ort 1, [ register 177 bit 1, register 16 bit 0 ] = [11], reserved [ 1 0 ], the port output queue is split into four priority queues or if map 802.1p to priority 0 - 3 mode. [ 01], the por t output queue is split into two priority queues or if map 802.1p to priority 0 - 3 mode. [ 00], single output queue on the port. there is no priority differentiation even though packets are classified into high or low priority. r/w 0 register 17 (0x11): p ort 1 control 1 register 33 (0x21): port 2 control 1 register 49 (0x31): port 3 control 1 register 65 (0x41): port 4 control 1 register 81 (0x51): port 5 control 1 address name description mode default 7 sniffer port 1, port is designated as sniffer port and will transmit packets that are monitored. 0, port is a normal port. r/w 0 6 receive sniff 1, all the packets received on the port will be marked as ?monitored packets? and forwarded to the designated ?sniffer port.? 0, no receive monitoring. r/w 0 5 transmit sniff 1, all the packets transmitted on the port will be marked as ?monitored packets? and forwarded to the designated ?sniffer port.? 0, no transmit monitoring. r/w 0 4 ? 0 port vlan membership define the port?s port vla n membersh ip. bit 4 stands for port 5, bit 3 for port 4...bit 0 for p ort 1. the port can only communicate within the membership. a ?1? includes a port in the membership, a ?0? excludes a port from membership. r/w 0x1f micrel, inc. ksz8895mq/rq/fmq january 22, 2013 66 r evision 1. 6 port registers (continued) register 18 (0x12 ): port 1 control 2 register 34 (0x22): port 2 control 2 register 50 (0x32): port 3 control 2 register 66 (0x42): port 4 control 2 register 82 (0x52): port 5 control 2 address name description mode default 7 user priority ceiling 1 , if packet ?s ?user priority field? is greater than the ?user priority field? in the port default tag register, replace the packet?s ?user priority field? with the ?user priority field? in the port default tag register control 3. 0, no replace packet ? s priority filed with po rt default tag priority filed of the port register control 3 bit[7:5]. r/w 0 6 ingress vlan filtering. 1, the switch will discard packet s whose vid port membership in vlan table bit[20:16] does not include the ingress port. 0, no ingress vlan filtering. r/w 0 5 discard non - pvid packets 1, the switch will discard packets whose vid does not match ingress port default vid. 0, no packets will be discarded. r/w 0 4 force flow control 1, will always enable rx and tx flow control on the port, regardless of an result. 0, the flow control is enabled based on an result (default) r/w 0 strap - in option led1_1/pcol for port 3/port 4 led1_1 default pull up (1): not force flow control; pcol default pull - down (0): not force flow control. led1_1 pull down (0): f orce flow control; pcol pull - up (1): force flow control. not e: led1_1 has internal pull - up; pcol have internal pull - down . 3 back pressure enable 1, enable port half - duplex back pressure. 0, disable port half - duplex back pressure. r/w pin pmrxd2 strap option. pull -d own (0): disable back pressure. pull - up(1): enable back pressure. not e: pmrxd2 has internal pull - down. 2 transmit enable 1, enable packet transmission on the port. 0, disable packet transmission on the port. r/w 1 1 receive enable 1, enable packet reception on the port. 0, disable packet reception on the port. r/w 1 0 learning disable 1, disable switch address learning capability. 0, enable switch address learning. r/w 0 not e: bits 2 - 0 are used for spanning tree support. see ? spanning tree support? section. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 67 r evision 1. 6 port registers (continued) register 19 (0x13): port 1 control 3 register 35 (0x23): port 2 control 3 register 51 (0x33): port 3 control 3 register 67 (0x43): port 4 control 3 register 83 (0x53): port 5 control 3 address na me description mode default 7 ? 0 default tag [15:8] port?s default tag, containing: 7 - 5: user priority bits 4: cfi bit 3 - 0 : vid[11:8] r/w 0x0 0 register 20 (0x14): port 1 control 4 register 36 (0x24): port 2 control 4 register 52 (0x34): port 3 c ontrol 4 register 68 (0x44): port 4 control 4 register 84 (0x54): port 5 control 4 address name description mode default 7 ? 0 default tag [7:0] default port 1?s tag, containing: 7 - 0: vid[7:0] r/w 0x0 1 not e: registers 19 and 20 (and those correspond ing to other ports) serve two purposes: (1) associated with the ingress untagged packets, and used for egress tagging; (2) default vid for the ingress untagged or null - vid - tagged packets, and used for address look up. register 87 (0x57): rmii management c ontrol register address name description mode default 7 ? 4 reserved n/a do not change . ro 0000 3 port 5 sw 5 - rmii 50mhz clock output disable ( used for ksz8895rq only ) disable the output of port 5 sw 5 - rmii 50 mhz output clock on rxc pin when 50mhz cloc k is not being used by the device and the 50mhz clock from external oscillator or opposite device in rmii mode 1 = disable clock output when rxc pin is not used in rmii mode 0 = enable clock output in rmii mode not e: mq/fmq is reserved with read only for t his bit. r/w 0 2 p5 - rmii 50mhz clock output disable ( used for ksz8895rq only ) disable the output of port 5 p5 - rmii 50 mhz output clock on rxc pin when 50mhz clock is not being used by the device and the 50mhz clock from external oscillator or opposite device in rmii mode 1 = disable clock output when rxc pin is not used in rmii mode 0 = enable clock output in rmii mode not e: mq/fmq is reserved with read only for this bit. r/w 0 1 ? 0 reserved n/a do not change . ro 00 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 68 r evision 1. 6 port registers (continued) regist er 25 (0x19): port 1 status 0 register 41 (0x29): port 2 status 0 register 57 (0x39): port 3 status 0 register 73 (0x49): port 4 status 0 register 89 (0x59): port 5 status 0 address name description mode default 7 hp_mdix 1 = hp auto mdi/mdi - x mode 0 = micrel auto mdi/mdi - x mode r/w 1 6 factory testing n/a do not change . ro 0 5 polrvs 1 = polarity is reversed 0 = polarity is not reversed ro 0 4 transmit flow control enable 1 = transmit flow control feature is active 0 = transmit flow control feature is inactive ro 0 3 receive flow control enable 1 = receive flow control feature is active 0 = receive flow control feature is inactive ro 0 2 operation speed 1 = link speed is 100mbps 0 = link speed is 10mbps ro 0 1 operation duplex 1 = link duplex is full 0 = link duplex is half ro 0 0 reserved n/a do not change . ro 0 register 26 (0x1a): port 1 phy special control/status register 42 (0x2a): port 2 phy special control/status register 58 (0x3a): port 3 phy special control/status register 74 (0x4a): po rt 4 phy special control/status register 90 (0x5a): port 5 phy special control/status address name description mode default 7 -4 reserved n/a do not change . ro 0 000 3 force_lnk 1 = force link pass 0 = normal operation r/w 0 2 pwrsave 1 = enable power saving 0 = disable power saving r/w 0 1 remote loopback 1 = perform remote loopback, loopback on port 1 as follows: port 1 (reg. 26, bit 1 = ?1?) start : rxp1/rxm1 (port 1) loopback: pmd/pma of port 1?s phy end: txp1/txm1 (port 1) setting reg. 42, 58, 74, 90, bit 1 = ?1? will perform remote loopback on port 2, 3, 4, 5. 0 = normal operation. r/w 0 0 reserved n/a do not change . ro 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 69 r evision 1. 6 port registers (continued) register 27 (0x1b): reserved register 43 (0x2b): reserved register 59 (0x3b): reserved register 75 (0x4b): reserved register 91 (0x5b): reserved address name description mode default 7 ? 0 reserved n/a do not change . ro 0 register 28 (0x1c): port 1 control 5 register 44 (0x2c): port 2 contro l 5 register 60 (0x3c): port 3 control 5 register 76 (0x4c): port 4 control 5 register 92 (0x5c): port 5 control 5 address name description mode default 7 disable auto - negotiation 1, disable auto - negotiation, speed and duplex are decided by bit 6 and 5 of the same register. 0, auto - negotiation is on. not e: the register bit value is the invert of the strap value at the pin. r/w 0 for port 3/p ort 4 only. invert of pins led[2][1]/led[5][0] strap option. pd(0): disable auto - negotiation. pu(1): enable auto - negotiation. not e: led[2][1]/led[5][0] have internal pull up. 6 forced speed 1, forced 100bt if an is disabled (bit 7). 0, forced 10bt if an is disabled (bit 7). r/w 1 5 forced duplex 1, forced full - duplex if (1) an is disabled or (2) an is enabled but failed. 0, forced half - duplex if (1) an is disabled or (2) an is enabled but failed (default). r/w 0 for port 3/p ort 4 only. pins led1_0/pcrs strap option : 1). f orce half - duplex mode : led1_0 pin pull - up(1) (default) for p ort 3 pcrs pin pull - down (0) (default) for p ort 4 2 ). f orce full - d uple x mode: led1_0 pin pull - down (0 ) for p ort 3 pcrs pull - up (1) for p ort 4. not e: led1_0 has internal pull - up; pcrs have internal pull down . micrel, inc. ksz8895mq/rq/fmq january 22, 2013 70 r evision 1. 6 port registers (continued) address name description mode default 4 advertised flow control capability 1, advertise flow control capability. 0, suppress flow control capability from transmission to link partner. r/w 1 3 advertised 100bt full - duplex capability 1, advertise 100bt full - dup lex capability. 0, suppress 100bt full - duplex capability from transmission to link partner. r/w 1 2 advertised 100bt half - duplex capability 1, advertise 100bt half - duplex capability. 0, suppress 100bt half - duplex capability from transmission to link partner. r/w 1 1 advertised 10bt full - duplex capability 1, advertise 10bt full - duplex capability. 0, suppress 10bt full - duplex capability from transmission to link partner. r/w 1 0 advertised 10bt half - duplex capability 1, advertise 10bt half - dupl ex capability. 0, suppress 10bt half - duplex capability from transmission to link partner. r/w 1 register 29 (0x1d): port 1 control 6 register 45 (0x2d): port 2 control 6 register 61 (0x3d): port 3 control 6 register 77 (0x4d): port 4 control 6 register 93 (0x5d): port 5 control 6 address name description mode default 7 led off 1, turn off all port?s leds (ledx_2, ledx_1, ledx_0, where ?x? is the port number). these pins will be driven high if this bit is set to one. 0, normal operation. r/w 0 6 txids 1, disable port?s transmitter. 0, normal operation. r/w 0 5 restart an 1, restart auto - negotiation. 0 , normal operation. r/w (sc) 0 4 fx reserved n/a ro 0 3 power down 1, power down. 0, normal operation. r/w 0 2 disable auto mdi/m di - x 1, disable auto mdi/mdi - x function. 0, enable auto mdi/mdi - x function. r/w 0 1 forced mdi 1, if auto mdi/mdi - x is disabled, force phy into mdi mode (transmit on rx pair) . 0, mdi - x mode (transmit on tx pair) . r/w 0 0 mac loopback 1 = perform mac loopback, loop back path as follows: e.g. set port 1 mac loopback (reg. 29, bit 0 = ?1?) , use port 2 as monitor port. the packets will transfer start: p ort 2 receiving ( also can start to receive packets from port 3, 4, 5 ). loop- back: p ort 1?s mac . e nd: port 2 transmitting ( also can end at p ort 3, 4, 5 respectively ). setting reg. 45, 61, 77, 93, bit 0 = ?1? will perform mac loopback on port 2, 3, 4, 5 respectively. 0 = normal operation. r/w 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 71 r evision 1. 6 port registers (continued) register 30 ( 0x1e): port 1 status 1 register 46 (0x2e): port 2 status 1 register 62 (0x3e): port 3 status 1 register 78 (0x4e): port 4 status 1 register 94 (0x5e): port 5 status 1 address name description mode default 7 mdix status 1, mdi. 0, mdi - x . ro 0 6 an done 1, an done. 0, an not done. ro 0 5 link good 1, link good. 0, link not good. ro 0 4 partner flow control capability 1, link partner flow control capable. 0, link partner not flow control capable. ro 0 3 partner 100bt full - duplex capabi lity 1, link partner 100bt full - duplex capable. 0, link partner not 100bt full - duplex capable. ro 0 2 partner 100bt half - duplex capability 1, link partner 100bt half - duplex capable. 0, link partner not 100bt half - duplex capable. ro 0 1 partner 10 bt full - duplex capability 1, link partner 10bt full - duplex capable. 0, link partner not 10bt full - duplex capable. ro 0 0 partner 10bt half - duplex capability 1, link partner 10bt half - duplex capable. 0, link partner not 10bt half - duplex capable. ro 0 register 31 (0x1f): port 1 control 7 and status 2 register 47 (0x2f): port 2 control 7 and status 2 register 63 (0x3f): port 3 control 7 and status 2 register 79 (0x4f): port 4 control 7 and status 2 register 95 (0x5f): port 5 control 7 and status 2 add ress name description mode default 7 phy loopback 1 = perform phy loopback, loop back path as follows: e.g. set p ort 1 phy loopback (reg. 31, bit 7 = ?1?) use the port 2 as monitor port. the packets will transfer . start: p ort 2 receiving ( also can start from port 3, 4, 5 ). loopback: pmd/pma of p ort 1?s phy end: port 2 transmitting ( also can end at p ort 3, 4, 5 respectively ). setting reg. 47, 63, 79, 95, bit 7 = ?1? will perform phy loopback on port 2, 3, 4, 5 res pectively. 0 = normal operation. r/w 0 6 reserved ro 0 5 phy isolate 1, electrical isolation of phy from mii/rmii and tx+/tx -. 0, normal operation. r/w 0 4 soft reset 1, phy soft reset. this bit is self clear. 0, normal operation. r/w (sc) 0 3 force link 1, force link in the phy. 0, normal operation r/w 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 72 r evision 1. 6 port registers (continued) address name description mode default 2 ? 0 port operation mode indication indicate the current state of port operation mode: [000] = r eseved [001] = still in auto - negotiation [010] = 10base - t half duplex [011] = 100base - tx half duplex [100] = r eserved [101] = 10base - t full duplex [110] = 100base - tx full duplex [111] = reserved ro 001 not e: port control 12 and 13, 14 and port status 1,2 contents can be access ed by miim (mdc/mdio) interface via the standard miim register definition. advanced control registers registers 104 to 109 define the switching engine?s mac address. this 48 - bit address is used as the source address in mac pause control frames . address name description mode default register 104 (0x68): mac address register 0 7 ? 0 maca[47:40] r/w 0x00 register 105 (0x69): mac address register 1 7 ? 0 maca[39:32] r/w 0x10 register 106 (0x6a): mac address register 2 7 ? 0 maca[31:24] r/w 0xa1 r egister 107 (0x6b): mac address register 3 7 ? 0 maca[23:16] r/w 0xff register 108 (0x6c): mac address register 4 7 ? 0 maca[15:8] r/w 0xff register 109 (0x6d): mac address register 5 7 ? 0 maca[7:0] r/w 0xff micrel, inc. ksz8895mq/rq/fmq january 22, 2013 73 r evision 1. 6 advanced control registers (continue d) use registers 110 and 111 to read or write data to the static mac address table, vlan table, dynamic address table, or the mib counters. address name description mode default register 110 (0x6e): indirect access control 0 7 ? 5 reserved reserved. r/w 000 4 read high write low 1, read cycle. 0, write cycle. r/w 0 3 ? 2 table select 00 = static mac address table selected. 01 = vlan table selected. 10 = dynamic address table selected. 11 = mib counter selected. r/w 0 1 ? 0 indirect address high bit 9 - 8 of indirect address. r/w 00 register 111 (0x6f): indirect access control 1 7 ? 0 indirect address low bit 7 - 0 of indirect address. r/w 00000000 not e: write to register 111 will actually trigger a command. read or write access will be decided by bit 4 of register 110. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 74 r evision 1. 6 advanced control registers (continued) address name description mode default register 112 (0x70): indirect data register 8 68? 64 indirect data bit 68 - 64 of indirect data. r/w 00000 register 113 (0x71): indirect data reg ister 7 63? 56 indirect data bit 63 - 56 of indirect data. r/w 00000000 register 114 (0x72): indirect data register 6 55? 48 indirect data bit 55 - 48 of indirect data. r/w 00000000 register 115 (0x73): indirect data register 5 47? 40 indirect data bit 47 - 40 of indirect data. r/w 00000000 register 116 (0x74): indirect data register 4 39? 32 indirect data bit 39 - 32 of indirect data. r/w 00000000 register 117 (0x75): indirect data register 3 31? 24 indirect data bit of 31 - 24 of indirect data r /w 00000000 register 118 (0x76): indirect data register 2 23? 16 indirect data bit 23 - 16 of indirect data. r/w 00000000 register 119 (0x77): indirect data register 1 15? 8 indirect data bit 15 - 8 of indirect data. r/w 00000000 register 120 (0x78): indirect data register 0 7 ? 0 indirect data bit 7 - 0 of indirect data. r/w 00000000 register 124 (0x7c): interrupt status register 7 ? 5 reserved reserved. ro 000 4 port 5 interrupt status 1, port 5 interrupt request 0, normal not e: this bit is set by p ort 5 link change. write a ?1? to clear this bit ro 0 3 port 4 interrupt status 1, port 4 interrupt request 0, normal not e: this bit is set by p ort 4 link change. write a ?1? to clear this bit ro 0 2 port 3 interrupt status 1, port 3 interrupt request 0, normal not e: this bit is set by p ort 3 link change. write a ?1? to clear this bit ro 0 1 port 2 interrupt status 1, port 2 interrupt request 0, normal not e: this bit is set by p ort 2 link change. write a ?1? to clear this bit ro 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 75 r evision 1. 6 advanced control registers (continued) address name description mode default 0 port 1 interrupt status 1, port 1 interrupt request 0, normal not e: this bit is set by p ort 1 link change. write a ?1? to clear this bit ro 0 register 125 (0x7d): interrupt mask register 7 ? 5 reserved reserved. ro 000 4 port 5 interrupt mask 1, enable port 5 interrupt . 0, normal r/w 0 3 port 4 interrupt mask 1, enable port 4 interrupt . 0, normal r/w 0 2 port 3 interrupt mask 1, enable port 3 interrupt . 0, normal r/w 0 1 port 2 interru pt mask 1, enable port 2 interrupt . 0, normal r/w 0 0 port 1 interrupt mask 1, enable port 1 interrupt . 0, normal r/w 0 the registers 128, 129 can be used to map from 802.1p priority field 0 - 7 to switch?s four priority queues 0 - 3 , 0x3 is highest priorit y queues as priority 3, 0x0 is lowest priority queues as priority 0. address name description mode default register 128 (0x80): global control 1 2 7 ? 6 tag_0x3 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 80 2.1p tag has a value of 0x3 . r/w 0x1 5 ? 4 tag_0x2 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x2 . r/w 0x1 3 ? 2 tag_0x1 ieee 802.1p mapping. the value in this field is used as the fra me?s priority when its ieee 802.1p tag has a value of 0x1 . r/w 0x0 1 ? 0 tag_0x0 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x0 . r/w 0x0 register 129 (0x81): global control 1 3 7 ? 6 t ag_0x7 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x7 . r/w 0x3 5 ? 4 tag_0x6 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x6 . r/w 0x3 3 ? 2 tag_0x5 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x5 . r/w 0x2 1 ? 0 tag_0x4 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x4 . r/w 0x2 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 76 r evision 1. 6 advanced control registers (continued) address name description mode default register 130 (0x82): global control 1 4 7 ? 6 pri_2q[1: 0 ] ( not e that program prio_2q[1:0] = 01 is not supported and shou ld be avoided) when the 2 queue s configuration is selected, these pri_2q[1: 0 ] bits are used to map the 2 - bit result of ieee 802.1p from register 128/129 or tos/diffserv from register 144 - 159 mapping (for 4 queues) into two queues low/high priorit ies . 2 -b it result of ieee 802.1p or tos/diffserv 00 (0) = map to low priority queue 01 (1) = prio_2q[0] map to low/high priority queue 10 (2) = prio_2q[1] map to low/high priority queue 11 (3) = map to high priority queue pri_2q[1:0] = 00: result 0,1,2 are low p riority. 3 is high priority. 10: result 0,1 are low priority. 2,3 are high priority (default). 11: result 0 is low priority. 1,2,3 are high priority. r/w 10 5 reserved n/a do not change . r o 0 4 reserved n/a do not change . ro 0 3 ? 2 reserved n/a do not c hange . ro 01 1 reserved n/a do not change . r o 0 0 reserved n/a do not change . r o 0 . register 131 (0x83): global control 1 5 7 reserved n/a ro 1 6 reserved n/a r o 0 5 unknown unicast packet forward 1 = enable supporting unknown unicast packet forward 0 = disable r/w 0 4 ? 0 unknown unicast packet forward port map 00000 = filter uknown unicast packet 00001 = forward uknown unicast packet to port 1. 00010 = forward uknown unicast packet to port 2. 00011 = forward uknown unicast packet to port 1, port 2 ?? 11111 = broadcast uknown unicast packet to all ports r/w 00000 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 77 r evision 1. 6 advanced control registers (continued) address name description mode default register 132 (0x84): global control 1 6 7 ? 6 chip i/o output drive strength select[1:0] output drive strength s elect[1:0] = 00 = 4ma drive strength 01 = 8ma drive strength (default) 10 = 12ma drive strength 11 = 16 ma drive strength not e: bit[1] value is the invert of the strap value at the pin. bit[0] value is the same of the strap value at the pin r/w 01 pin led [3][0] strap option. pull - down (0): select 12ma drive strength. pull - up (1): select 8ma drive strength. not e: led[3][0] has internal pull - up. 5 unknown multicast packet forward ( not including ip multicast packet) 1 = enable supporting unknown multicast pa cket forward 0 = disable r/w 0 4 ? 0 unknown multicast packet forward port map 00000 = filter uknown multiicast packet 00001 = forward uknown multicast packet to port 1 . 00010 = forward uknown multicast packet to port 2. 00011 = forward uknown multicast pac ket to port 1, port 2 ?? 11111 = broadcast uknown multicast packet to all ports r/w 00000 register 133(0x85): global control 1 7 7 ? 6 reserved ro 00 5 unknown vid packet forward 1 = enable supporting unknown vid packet forward 0 = disable r/w 0 4 ? 0 unkn own vid packet forward port map 00000 = filter uknown vid packet 00001 = forward uknown vid packet to port 1 . 00010 = forward uknown vid packet to port 2. 00011 = forward uknown vid packet to port 1, port 2 ?? 11111 = broadcast uknown vid packet to all por ts r/w 00000 register 134 (0x86): global control 1 8 7 reserved n/a ro 0 6 self address filter enable 1 = enable filtering of self - address unicast and multicast packet 0 = do not filter self - address packet not e: the self - address filtering will filter pa ckets on the egress port , self mac address is assigned in the register 104 - 109. r/w 0 5 unknown ip multicast packet forward 1 = enable supporting unknown ip multicast packet forward 0 = disable r/w 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 78 r evision 1. 6 advanced control registers (continued) address na me description mode default 4 ? 0 unknown ip multicast packet forward port map 00000 = filter uknown ip multiicast packet 00001 = forward uknown ip multicast packet to port 1 . 00010 = forward uknown ip multicast packet to port 2 . 00011 = forward uknown ip multicast packet to port 1, port 2 ?? 11111 = broadcast uknown ip multicast packet to all ports r/w 00000 register 135 (0x87): global control 1 9 7 reserved n/a do not change . ro 0 6 reserved n/a do not change . r o 0 5 ? 4 ingress rate limit period the un it period for calculating ingress rate limit 00 = 16 ms 01 = 64 ms 1x = 256 ms r/w 01 3 queue - based egress rate limit enabled enable queue - based egress rate limit 0 = port - base egress rate limit (default) 1 = queue - based egress rate limit r/w 0 2 inser tion source port pvid tag selection enable 1 = enable source port pvid tag insertion or non - insertion option on the egress port for each source port pvid based on the port s register s control 8. 0 = disable , all packets from any ingress port will be inserte d pvid based on port register control 0 bit 2. r/w 0 1 ? 0 reserved n/a do not change ro 00 register 144 (0x90): tos priority control register 0 the ipv4/ipv6 tos priority control registers implement a fully decoded 64 bit differentiated services code poi nt (dscp) register used to determine priority from the 6 bit tos field in the ip header. the most significant 6 bits of the tos field are fully decoded into 64 possibilities, and the singular code that results is mapped to the value in the corresponding bi t in the dscp register. 7 ? 6 dscp[7:6] ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when bits[7:2] of the frame?s ip tos/diffserv/traffic class value is 0x0 3 r/w 00 5 ? 4 dscp[5:4] ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when bits[7:2] of the frame?s ip tos/diffserv/traffic class value is 0x0 2 r/w 00 3 ? 2 dscp[3:2] ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when bits[7:2] of the frame?s ip tos/diffse rv/traffic class value is 0x0 1 r/w 00 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 79 r evision 1. 6 advanced control registers (continued) address name description mode default 1 ? 0 dscp[1:0] ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when bits[7:2] of the frame?s ip tos/diff serv/traffic class value is 0x00 r/w 00 register 145 (0x91): tos priority control register 1 7 ? 6 dscp[15:14] ipv4 and ipv6 mapping _ for value 0x 07 r/w 00 5 ? 4 dscp[13:12] ipv4 and ipv6 mapping _ for value 0x 06 r/w 00 3 ? 2 dscp[11:10] ipv4 and ipv6 ma pping _ for value 0x 05 r/w 00 1 ? 0 dscp[9:8] ipv4 and ipv6 mapping _ for value 0x 04 r/w 00 register 146 (0x92): tos priority control register 2 7 ? 6 dscp[23:22] ipv4 and ipv6 mapping _ for value 0x 0b r/w 00 5 ? 4 dscp[21:20] ipv4 and ipv6 mapping _ for value 0x 0a r/w 00 3 ? 2 dscp[19:18] ipv4 and ipv6 mapping _ for value 0x 09 r/w 00 1 ? 0 dscp[17:16] ipv4 and ipv6 mapping _ for value 0x 08 r/w 00 register 147 (0x93): tos priority control register 3 7 ? 6 dscp[31:30] ipv4 and ipv6 mapping _ for value 0x 0f r/w 00 5 ? 4 dscp[29:28] ipv4 and ipv6 mapping _ for value 0x 0e r/w 00 3 ? 2 dscp[27:26] ipv4 and ipv6 mapping _ for value 0x 0d r/w 00 1 ? 0 dscp[25:24] ipv4 and ipv6 mapping _ for value 0x 0c r/w 00 register 148 (0x94): tos priority control register 4 7 ? 6 dscp[39:38] ipv4 and ipv6 mapping _ for value 0x 13 r/w 00 5 ? 4 dscp[37:36] ipv4 and ipv6 mapping _ for value 0x 12 r/w 00 3 ? 2 dscp[35:34] ipv4 and ipv6 mapping _ for value 0x 11 r/w 00 1 ? 0 dscp[33:32] ipv4 and ipv6 mapping _ for value 0x 1 0 r/w 00 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 80 r evision 1. 6 advanced control registers (continued) register 149 (0x95): tos priority control register 5 7 ? 6 dscp[47:46] ipv4 and ipv6 mapping _ for value 0x 17 r/w 00 5 ? 4 dscp[45:44] ipv4 and ipv6 mapping _ for value 0x 16 r/w 00 3 ? 2 dscp[43:42] ipv4 and ipv6 mapp ing _ for value 0x 15 r/w 00 1 ? 0 dscp[41:40] ipv4 and ipv6 mapping _ for value 0x 14 r/w 00 register 150 (0x96): tos priority control register 6 7 ? 6 dscp[55:54] ipv4 and ipv6 mapping _ for value 0x 1b r/w 00 5 ? 4 dscp[53:52] ipv4 and ipv6 mapping _ for value 0x 1a r/w 00 3 ? 2 dscp[51:50] ipv4 and ipv6 mapping _ for value 0x 19 r/w 00 1 ? 0 dscp[49:48] ipv4 and ipv6 mapping _ for value 0x 18 r/w 00 register 151 (0x97): tos priority control register 7 7 ? 6 dscp[63:62] ipv4 and ipv6 mapping _ for value 0x 1f r/w 00 5 ? 4 dscp[61:60] ipv4 and ipv6 mapping _ for value 0x 1e r/w 00 3 ? 2 dscp[59:58] ipv4 and ipv6 mapping _ for value 0x 1d r/w 00 1 ? 0 dscp[57:56] ipv4 and ipv6 mapping _ for value 0x 1c r/w 00 register 152 (0x98): tos priority control register 8 7 ? 6 dscp[71:70] ipv4 and ipv6 mapping _ for value 0x 23 r/w 00 5 ? 4 dscp[69:68] ipv4 and ipv6 mapping _ for value 0x 22 r/w 00 3 ? 2 dscp[67:66] ipv4 and ipv6 mapping _ for value 0x 21 r/w 00 1 ? 0 dscp[65:64] ipv4 and ipv6 mapping _ for value 0x 2 0 r/w 00 register 153 (0x99): tos priority control register 9 7 ? 6 dscp[79:78] ipv4 and ipv6 mapping _ for value 0x 27 r/w 00 5 ? 4 dscp[77:76] ipv4 and ipv6 mapping _ for value 0x 26 r/w 00 3 ? 2 dscp[75:74] ipv4 and ipv6 mapping _ for value 0x 25 r/w 00 1 ? 0 dscp[7 3:72] ipv4 and ipv6 mapping _ for value 0x 24 r/w 00 register 154 (0x9a): tos priority control register 10 7 ? 6 dscp[87:86] ipv4 and ipv6 mapping _ for value 0x 2b r/w 00 5 ? 4 dscp[85:84] ipv4 and ipv6 mapping _ for value 0x 2a r/w 00 3 ? 2 dscp[83:82] ip v4 and ipv6 mapping _ for value 0x 29 r/w 00 1 ? 0 dscp[81:80] ipv4 and ipv6 mapping _ for value 0x 28 r/w 00 register 155 (0x9b): tos priority control register 11 7 ? 6 dscp[95:94] ipv4 and ipv6 mapping _ for value 0x 2f r/w 00 5 ? 4 dscp[93:92] ipv4 and ip v6 mapping _ for value 0x 2e r/w 00 3 ? 2 dscp[91:90] ipv4 and ipv6 mapping _ for value 0x 2d r/w 00 1 ? 0 dscp[89:88] ipv4 and ipv6 mapping _ for value 0x 2c r/w 00 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 81 r evision 1. 6 advanced control registers (continued) address name description mode default register 1 56 (0x9c): tos priority control register 12 7 ? 6 dscp[103:102] ipv4 and ipv6 mapping _ for value 0x 33 r/w 00 5 ? 4 dscp[101:100] ipv4 and ipv6 mapping _ for value 0x 32 r/w 00 3 ? 2 dscp[99:98] ipv4 and ipv6 mapping _ for value 0x 31 r/w 00 1 ? 0 dscp[97:96] ipv4 and ipv6 mapping _ for value 0x 3 0 r/w 00 register 157 (0x9d): tos priority control register 13 7 ? 6 dscp[111:110] ipv4 and ipv6 mapping _ for value 0x 37 r/w 00 5 ? 4 dscp[109:108] ipv4 and ipv6 mapping _ for value 0x 36 r/w 00 3 ? 2 dscp[107:106] i pv4 and ipv6 mapping _ for value 0x 35 r/w 00 1 ? 0 dscp[105:104] ipv4 and ipv6 mapping _ for value 0x 34 r/w 00 register 158 (0x9e): tos priority control register 14 7 ? 6 dscp[119:118] ipv4 and ipv6 mapping _ for value 0x 3b r/w 00 5 ? 4 dscp[117:116] ipv4 and ipv6 mapping _ for value 0x 3a r/w 00 3 ? 2 dscp[115:114] ipv4 and ipv6 mapping _ for value 0x 39 r/w 00 1 ? 0 dscp[113:112] ipv4 and ipv6 mapping _ for value 0x 38 r/w 00 register 159 (0x9f): tos priority control register 15 7 ? 6 dscp[127:126] ipv4 an d ipv6 mapping _ for value 0x 3f r/w 00 5 ? 4 dscp[125:124] ipv4 and ipv6 mapping _ for value 0x 3e r/w 00 3 ? 2 dscp[123:122] ipv4 and ipv6 mapping _ for value 0x 3d r/w 00 1 ? 0 dscp[121:120] ipv4 and ipv6 mapping _ for value 0x 3c r/w 00 register 1 65 (0 xa5 ): fiber control register 7 ? 6 reserved n/a do not change ro 000 5 fmq fiber mode enable 1 = mq/rq device (default) 0 = fmq device (fiber mode) r/w 1 4 ? 0 reserved n/a do not change ro 10000 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 82 r evision 1. 6 advanced control registers (continued) address name descript ion mode default register 176 (0xb0): port 1 control 8 register 192 (0xc0): port 2 control 8 register 208 (0xd0): port 3 control 8 register 224 (0xe0): port 4 control 8 register 240 (0xf0): port 5 control 8 7 ? 4 reserved ro 0000 3 insert source port pv id for untagged packet destination to highest egress port not e: enabled by the register 135 bit 2 register 176: insert source p ort 1 pvi d for untagged frame at egress p ort 5 register 192: insert source p ort 2 pvid for untagged frame at egress p ort 5 regi ster 208: insert source p ort 3 pvid for untagged frame at egress p ort 5 register 224: insert source p ort 4 pvid for untagged frame at egress p ort 5 register 240: insert source p ort 5 pvid for untagged frame at egress p ort 4 r/w 0 2 insert source port pvid for untagged packet destination to second highest egress port not e: enabled by the register 135 bit 2 register 176: insert source p ort 1 pvid for untagged frame at egress p p ort 4 register 192: insert source p ort 2 pvid for untagged frame at egress p ort 4 register 208: insert source p ort 3 pvid for untagged frame at egress p ort 4 register 224: insert source p ort 4 pvid for untagged frame at egress p ort 3 register 240: insert source p ort 5 pvid for untagged frame at egress p ort 3 r/w 0 1 insert source por t pvid for untagged packet destination to second lowest egress port not e: enabled by the register 135 bit 2 register 176: insert source p ort 1 pvid for untagged frame at egress p ort 3 register 192: insert source p ort 2 pvid for untagged frame at egress p ort 3 register 208: insert source p ort 3 pvid for untagged frame at egress p ort 2 register 224: insert source p ort 4 pvid for untagged frame at egress p ort 2 register 240: insert source p ort 5 pvid for untagged frame at egress p ort 2 r/w 0 0 insert source port pvid for untagged packet destination to lowest egress port not e: enabled by the register 135 bit 2 register 176: insert source p ort 1 pvid for untagged frame at egress p ort 2 register 192: insert source p ort 2 pvid for untagged frame at egress p ort 1 register 208: insert source p ort 3 pvid for untagged frame at egress p ort 1 register 224: insert source p ort 4 pvid for untagged frame at egress p ort 1 register 240: insert source p ort 5 pvid for untagged frame at egress p ort 1 r/w 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 83 r evision 1. 6 advanced control registers (continued) address name description mode default register 177 (0xb1): port 1 control 9 register 193 (0xc1): port 2 control 9 register 209 (0xd1): port 3 control 9 register 225 (0xe1): port 4 control 9 register 241 (0xf1): port 5 control 9 7 ? 2 reserved ro 0000000 1 4 queue split enable this bit in combination with register16/32/48/64/80 bit 0 will select the split of ? /4 queues: {register177 bit 1, register16 bit 0} = 11, reserved. 1 0 , the port output queue is split into four priority queue s or if map 802.1p to priority 0 - 3 mode. 01, the port output queue is split into two priority queues or if map 802.1p to priority 0 - 3 mode. 00, single output queue on the port. there is no priority differentiation even though packets are classified into hi gh and low priority . r/w 0 0 enable dropping tag 0 = normal 1 = enable the drop received tagged packets r/w 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 84 r evision 1. 6 advanced control registers (continued) address name description mode default register 178 (0xb2): port 1 control 10 register 194 (0xc2): port 2 control 10 register 210 (0xd2): port 3 control 10 register 226 (0xe2): port 4 control 10 register 242 (0xf2): port 5 control 10 7 enable port transmit queue 3 ratio 0, strict priority, will transmit all the packets from this priority queue 3 befo re transmit lower priority queue. 1, bit[6:0] reflect the packet number allow to transmit from this priority queue 3 within a certain time . r/w 1 6 ?0 port transmit queue 3 ratio[6:0] p acket number for transmit queue 3 for highest priority packets in four queues mode . r/w 0001000 register 179 (0xb3): port 1 control 11 register 195 (0xc3): port 2 control 11 register 211 (0xd3): port 3 control 11 register 227 (0xe3): port 4 control 11 register 243 (0xf3): port 5 control 11 7 enable port transmit queue 2 ra tio 0, strict priority, will transmit all the packets from this priority queue 2 before transmit lower priority queue. 1, bit[6:0] reflect the packet number allow to transmit from this priority queue 1 within a certain time . r/w 1 6 ?0 port transmit queue 2 ratio[6:0] p acket number for transmit queue 2 for high /low priority packets in high /low priority packets in four queues mode . r/w 0000100 register 180 (0xb4): port 1 control 12 register 196 (0xc4): port 2 control 12 register 212 (0xd4): port 3 control 12 register 228 (0xe4): port 4 control 12 register 244 (0xf4): port 5 control 12 7 enable port transmit queue 1 rate 0, strict priority, will transmit all the packets from this priority queue 1 before transmit lower priority queue. 1 , bit[6:0] reflect th e packet number allow to transmit from this priority queue 1 within a certain time . r/w 1 6 ?0 port transmit queue 1 ratio[6:0] p acket number for transmit queue 1 for low / high priority packets in four queues mode and high priority packets in two queues mod e . r/w 0000010 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 85 r evision 1. 6 advanced control registers (continued) address name description mode default register 181 (0xb5): port 1 control 13 register 197 (0xc5): port 2 control 13 register 213 (0xd5): port 3 control 13 register 229 (0xe5): port 4 control 13 r egister 245 (0xf5): port 5 control 13 7 enable port transmit queue 0 rate 0, strict priority, will transmit all the packets from this priority queue 0 before transmit lower priority queue. 1, bit[6:0] reflect the packet number allow to transmit from this priority queue 0 within a certain time . r/w 1 6 ?0 port transmit queue 0 ratio[6:0] packet number for transmit queue 0 for low est priority packets in four queues mode and low priority packets in two queues mode . r/w 0000001 register 182 (0xb6): port 1 ra te limit control register 198 (0xc6): port 2 rate limit control register 214 (0xd6): port 3 rate limit control register 230 (0xe6): port 4 rate limit control register 246 (0xf6): port 5 rate limit control 7 ? 5 reserved ro 000 4 ingress rate limit flow co ntrol enable 1 = flow control is asserted if the port?s receive rate is exceeded . 0 = flow control is not asserted if the port?s receive rate is exceeded . r/w 0 3 ? 2 limit mode ingress limit mode these bits determine what kinds of frames are limited and co unted against ingress rate limiting. = 00, limit and count all frames . = 01, limit and count broadcast, multicast, and flooded unicast frames . = 10, limit and count broadcast and multicast frames only . = 11, limit and count broadcast frames only . r/w 0 0 1 count ifg count ifg bytes = 1, each frame?s minimum inter frame gap . (ifg) bytes (12 per frame) are included in ingress and egress rate limiting calculations. = 0, ifg bytes are not counted. r/w 0 0 co unt pre count preamble bytes = 1, each frame?s preamble bytes (8 per frame) are included in ingress and egress rate limiting calculations. = 0, preamble bytes are not counted. r/w 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 86 r evision 1. 6 advanced control registers (continued) address name description mode default register 183 (0xb7): port 1 priorit y 0 ingress limit control 1 register 199 (0xc7): port 2 priority 0 ingress limit control 1 register 215 (0xd7): port 3 priority 0 ingress limit control 1 register 231 (0xe7): port 4 priority 0 ingress limit control 1 register 247 (0xf7): port 5 priority 0 ingress limit control 1 7 reserved ro 0 6 ? 0 port based priority 0 ingress limit ingress data rate limit for priority 0 frames ingress traffic from this port is shaped according to the data rate selected table. see the table follow ing the end of egress l imit control registers . r/w 0000000 register 184 (0xb8): port 1 priority 1 ingress limit control 2 register 200 (0xc8): port 2 priority 1 ingress limit control 2 register 216 (0xd8): port 3 priority 1 ingress limit control 2 register 232 (0xe8): port 4 pr iority 1 ingress limit control 2 register 248 (0xf8): port 5 priority 1 ingress limit control 2 7 reserved ro 0 6 ? 0 port based priority 1 ingress limit ingress data rate limit for priority 1 frames ingress traffic from this port is shaped according to t he data rate selected table. see the table follow ing the end of egress limit control registers . r/w 0000000 register 185 (0xb9): port 1 priority 2 ingress limit control 3 register 201 (0xc9): port 2 priority 2 ingress limit control 3 register 217 (0xd9): port 3 priority 2 ingress limit control 3 register 233 (0xe9): port 4 priority 2 ingress limit control 3 register 249 (0xf9): port 5 priority 2 ingress limit control 3 7 reserved ro 0 6 ? 0 port - based priority 2 ingress limit ingress data rate limit for p riority 2 frames ingress traffic from this port is shaped according to the data rate selected table. see the table follow the end of egress limit control registers . r/w 0000000 register 186 (0xba): port 1 priority 3 ingress limit control 4 register 202 (0 xca): port 2 priority 3 ingress limit control 4 register 218 (0xda): port 3 priority 3 ingress limit control 4 register 234 (0xea): port 4 priority 3 ingress limit control 4 register 250 (0xfa): port 5 priority 3 ingress limit control 4 7 reserved ro 0 6 ? 0 port - based priority 3 ingress limit ingress data rate limit for priority 3 frames ingress traffic from this port is shaped according to the data rate selected table. see the table follow the end of egress limit control registers . r/w 0000000 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 87 r evision 1. 6 advance d control registers (continued) address name description mode default register 187 (0xbb): port 1 queue 0 egress limit control 1 register 203 (0xcb): port 2 queue 0 egress limit control 1 register 219 (0xdb): port 3 queue 0 egress limit control 1 regis ter 235 (0xeb): port 4 queue 0 egress limit control 1 register 251 (0xfb): port 5 queue 0 egress limit control 1 7 reserved ro 0 6 ? 0 port queue 0 egress limit egress data rate limit for priority 0 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follow the end of egress limit control registers . in four queues mode, it is lowest priority. in two q ueues mode, it is low priority. r/w 0000000 register 188 (0xbc) : port 1 queue 1 egress limit c ontrol 2 register 204 (0xcc) : port 2 queue 1 egress limit control 2 register 220 (0xdc) : port 3 queue 1 egress limit control 2 register 236 (0xec) : port 4 queue 1 egress limit control 2 register 252 (0xfc) : port 5 queue 1 egress limit control 2 7 rese rved ro 0 6 ? 0 port queue 1 egress limit egress data rate limit for priority 1 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follow the end of egress limit control registers . in four queu es mode, it is low/high priority. in two qu eues mode, it is high priority. r/w 0000000 register 189 (0xbd): port 1 queue 2 egress limit control 3 register 205 (0xcd): port 2 queue 2 egress limit control 3 register 221 (0xdd): port 3 queue 2 egress limit c ontrol 3 register 237 (0xed): port 4 queue 2 egress limit control 3 register 253 (0xfd): port 5 queue 2 egress limit control 3 7 reserved ro 0 6 ? 0 port queue 2 egress limit egress data rate limit for priority 2 frames egress traffic from this priority q ueue is shaped according to the data rate selected table. see the table follow the end of egress limit control registers . in four queues mode, it is high/low priority. r/w 0000000 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 88 r evision 1. 6 advanced control registers (continued) address name description mode d efault register 190 (0xbe) : port 1 queue 3 egress limit control 4 register 206 (0xce) : port 2 queue 3 egress limit control 4 register 222 (0xde) : port 3 queue 3 egress limit control 4 register 238 (0xee): port 4 queue 3 egress limit control 4 register 254 (0xfe): port 5 queue 3 egress limit control 4 7 reserved ro 0 6 ? 0 port queue 3 egress limit egress data rate limit for priority 3 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follo w the end of egress limit control registers . in four queues mode, it is highest priority. r/w 0000000 not e s : 1. in t he port priority 0 ? 3 ingress rate limit mode, will need to set all related ingress/egress ports to two queues or four queues mode . 2. in t he port queue 0 ? 3 egress rate limit mode, the highest priority get exact rate limit based on the rate select table, other priorities packets rate are based upon the ratio of the port register control 10/11/12/13 when use more than one egress queue per port. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 89 r evision 1. 6 dat a rate selection table in 100bt rate for 100bt mode priority/ queue 0 - 3 ingress/egress limit control register bit [6:0 ] = decimal 1 mbps <= rate <= 99 mbps rate( decimal integer 1 - 99 ) rate = 100 mbps 0 or 100 (decimal), ?0? is default value less than 1mbps see as below decimal 64 kbps 7?d101 128 kbps 7?d102 192 kbps 7?d103 256 kbps 7?d104 320 kbps 7?d105 384 kbps 7?d106 448 kbps 7?d107 512 kbps 7?d108 576 kbps 7?d109 640 kbps 7?d110 704 kbps 7?d111 768 kbps 7?d112 832 kbps 7?d113 896 kbps 7?d1 14 960 kbps 7?d115 table 13. 100bt rate selection for the rate limit data rate selection table in 10bt rate for 10bt mode priority/ queue 0 - 3 ingress/egress limit control register bit [6:0 ] = decimal 1 mbps <= rate <= 9 mbps rate( decimal integer 1 - 9 ) rate = 10 mbps 0 or 10 (decimal), ?0? is default value less than 1mbps see as below decimal 64 kbps 7?d101 128 kbps 7?d102 192 kbps 7?d103 256 kbps 7?d104 320 kbps 7?d105 384 kbps 7?d106 448 kbps 7?d107 512 kbps 7?d108 576 k bps 7?d109 640 kbps 7?d110 704 kbps 7?d111 768 kbps 7?d112 832 kbps 7?d113 896 kbps 7?d114 960 kbps 7?d115 table 14. 10bt rate selection for the rate limit micrel, inc. ksz8895mq/rq/fmq january 22, 2013 90 r evision 1. 6 address name description mode default register 191(0xbf): te sting register 7 ? 0 reserved n/a r o 0x80 register 207(0xcf): reserved control register 7 ? 0 reserved n/a do not change . r o 0x15 register 223(0xdf): test register 2 7 ?0 reserved r/w 0x0c register 239(0xef): test register 3 7 ? 0 reserved n/a do not ch ange. r o 0 x32 register 255(0xff): testing register 4 7 reserved n/a do not change . r o 0 6 invert phase of smtxc clock input for sw5 - rmii (used for ksz8895rq only) 1 = invert the phase of smtxc clock input in rmii mode , set this bit at normal mode device when connect two devices with sw5 - rmii back to back connection case only . please see strap pin led2_2 for normal mode. 0 = normal phase if smtxc clock input not e: mq/fmq are reserved with read only for this bit. r/w 0 5 ? 0 reserved n/a do not change . r o 0 00000 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 91 r evision 1. 6 static mac address table ksz8895mq/rq/fmq has a static and a dynamic address table. when a da look - up is requested, both tables will be searched to make a packet forwarding decision. when an sa look - up is requested, only the dynamic table is searc hed for aging, migration, and learning purposes. the static da look - up result will have precedence over the dynamic da look - up result. if there are da matches in both tables, the result from the static table will be used. the static table can only be acces sed and controlled by an external spi master (usually a processor). the entries in the static table will not be aged out by ksz8895mq/rq/fmq . an external device does all addition, modification and deletion. not e: register bit assignments are different for static mac table reads and static mac table write, as shown in table 15 . address name description mode default format of static mac table for reads ( 32 entries) 63? 57 fid filter vlan id, representing one of the 128 active vlans . ro 0000 000 56 use f id 1, use (fid+mac) to look - up in static table. 0, use mac only to look - up in static table. ro 0 55 reserved reserved. ro n/a 54 override 1, override spanning tree ?transmit enable = 0? or ?receive enable = 0* setting. this bit is used for spanning tree implementation. 0, no override. ro 0 53 valid 1, this entry is valid, the look - up result will be used. 0, this entry is not valid. ro 0 52? 48 forwarding ports the 5 bits control the forward por ts, example: 00001, forward to port 1 00010, forward to p ort 2 ?.. 10000, forwar d to port 5 00110, forward to port 2 and p ort 3 11111, broadcasting (excluding the ingress port) ro 00000 47? 0 mac address (da) 48 bit mac address. ro 0x0 format of static mac table for writes ( 32 entries) 62? 56 fid filter vlan id, representing one of the 1 28 active vlans. w 0000 000 55 use fid 1, use (fid+mac) to look - up in static table. 0, use mac only to look - up in static table. w 0 54 override 1, override spanning tree ?transmit enable = 0? or ?receive enable = 0? setting. this bit is used for spanning tree implementation. 0, no override. w 0 53 valid 1, this entry is valid, the look - up result will be used. 0, this entry is not valid. w 0 52? 48 forwarding ports the 5 bits control the forward ports, example: 00001, f orwa rd top ort 1 00 010, forward to p ort 2 ..... 10000, forward to p ort 5 00110, forward to port 2 and p ort 3 11111, broadcasting (excluding the ingress port) w 00000 47? 0 mac address (da) 48- bit mac address. w 0x0 table 15. st atic mac address table micrel, inc. ksz8895mq/rq/fmq january 22, 2013 92 r evision 1. 6 examples: (1) static address table read (read the 2 nd entry) write to register 110 with 0x10 (read static table selected) write to register 111 with 0x1 (trigger the read operation) then read register 113 (6 3 - 56) read register 114 (5 5 - 48) read register 115 (47 - 40) read register 116 (39 - 32) read register 117 (31 - 24) read register 118 (23 - 16) read register 119 (15 - 8) read register 120 (7 - 0) (2) static address table write (write the 8 th entry) write to register 110 with 0x10 (read stat ic table selected) write register 113 (62 - 56) write register 114 (55 - 48) write register 115 (47 - 40) write register 116 (39 - 32) write register 117 (31 - 24) write register 118 (23 - 16) write register 119 (15 - 8) write register 120 (7 - 0) write to registe r 110 with 0x00 (write static table selected) write to register 111 with 0x7 (trigger the write operation) micrel, inc. ksz8895mq/rq/fmq january 22, 2013 93 r evision 1. 6 vlan table the vlan table is used for vlan table look - up. if 802.1q vlan mode is enabled (register 5 bit 7 = 1), this table is used to retrieve vla n information that is associated with the ingress packet. there are three fields for fid (filter id), valid , and vlan membership in the vlan table . t he three fields must be initialized before the table is used . there is no vid field because 4096 vids are u sed as a dedicated memory address index into a 1024x52 - bit memory spac e. e ach entry has four vlans . e ach vlan has 13 bits . f our vlans need 52 bits . t here are a total of 1024 entries to support a total of 4096 vlan id s by using dedicated memory address and data bits . r efer to table 17 for detail s . fid has 7 - bit s to support 128 active vlans. address name description mode initial value suggestion format of static vlan table (support max 4096 vlan id entries and 128 active vlans) 12 valid 1, the entry is valid. 0, entry is invalid. r/w 0 11? 7 membership specif ies which ports are members of the vlan. if a da look - up fails (no match in both static and dynamic tables), the packet associated with this vlan will be forwarded to ports specified in this field. e.g., 11001 means p ort s 5, 4, and 1 are in this vlan. r/w 11111 6 ? 0 fid filter id. ksz8895mq/rq/fmq supports 128 active vlans represented by these seven bit fields. fid is the mapped id. if 802.1q vlan is enabled, the look - up will be based on f id+da and fid+sa. r/w 0 table 16. vlan table if 802.1q vlan mode is enabled, ksz8895mq/rq/fmq assigns a vid to every ingress packet when the packet is untagged or tagged with a null vid, the packet is assigned with the default por t vid of the ingress port. if the packet is tagged with non - null vid, the vid in the tag is used. the look - up process starts from the vlan table look - up based on vid number with its dedicated memory address and data bits . if the entry is not valid in the v lan table , the packet is dropped and no address learning occurs. if the entry is valid, the fid is retrieved. the fid+da and fid+sa lookups in mac tables are performed. the fid+da look - up determines the forwarding ports. if fid+da fails for look - up in the mac table , the packet is broadcast to all the members or specified members (excluding the ingress port) based on the vlan table . if fid+sa fails, the fid+sa is learned. t o communicate between different active vlans, set the same fid ; otherwise set a differ ent fid. the vlan table configuration is organized as 1024 vlan sets, each vlan set consists of four vlan entries, to support up to 4096 vlan entries. each vlan set has 52 bits and should be read or written at the same time specified by the indirect addres s. the vlan entries in the vlan set are mapped to indirect data registers as follow: ? entry0[12:0] maps to the vlan set bits[12 - 0] {register119[4:0], register120[7:0]} ? entry1[12:0] maps to the vlan set bits[25 - 13]{register117[1:0], register118[7:0], regis ter119[7:5]} ? entry2[12:0] maps to the vlan set bits[38 - 26]{register116[6:0], register117[7:2]} ? entry3[12:0] maps to the vlan set bits[51 - 39]{register114[3:0], register115[7:0], register116[7]} in order to read one vlan entry, the vlan set is read first and the specific vlan entry information can be extracted. to update any vlan entry, the vlan set is read first then only the desired vlan entry is updated and the whole vlan set is written back. the fid in the vlan table is 7 - bit, so the vlan table support s unique 128 flow vlan groups. each vlan set address is 10 bits long (maximu m is 1024) in the indirect address register 110 and 111 , the bit [9 - 8] of vlan set address is at bit [1 - 0] of register 110, a nd the bit [7 - 0] of vlan set address is at bit [7 - 0] of reg ister 111. each write and read can access up to four consecutive vlan entries . micrel, inc. ksz8895mq/rq/fmq january 22, 2013 94 r evision 1. 6 examples: (1) vlan table read (read the vid = 2 entry ) write the indirect control and address registers first write to register 110 (0x6e) with 0x14 (read vlan tab le selected) write to register 111 (0x6f) with 0x0 (trigger the read operation for vid = 0, 1, 2, 3 entries ) then read t he indirect data registers bits [38 - 26] for vid = 2 entry read register 116 (0x74), (register116[6:0] are bits 12 - 6 of vlan vid = 2 entry ) read register 117 (0x75), (register117[7:2] are bits 5 - 0 of vlan vid = 2 entry) (2) vlan table write (write the vid = 10 entry) read the vlan set that contains vid = 8, 9, 10, 11 . write to register 110 (0x6e) with 0x14 (re ad vlan table selected) write to register 111 (0x6f) with 0x02 (trigger the read operation and vid = 8, 9, 10, 11 indirect address) read the vlan set first by the indirect data registers 114, 115, 116, 117, 118, 119, 120 . modify t he indirect data registers bits [38 - 26] by the register 116 bit[6 - 0] and register 117 bit [7 - 2] as follows: write to register 116 (0x74), (register116[6:0] are bits 12 - 6 of vlan vid = 10 entry ) write to register 117 (0x75), (register117[7:2] are bits 5 - 0 of vlan vid = 10 entry) then write the indirect control and address registers write to register 110 (0x6e) with 0x04 (write vlan table selected) write to register 111 (0x6f) with 0x 0 2 (trigger the write operation an d vid = 8, 9, 10, 11 indirect address ) table 17 shows the relationship of the indirect address/data registers and vlan id. indirect address high/low bit[9 - 0] for vlan sets indirect data registe r s bits for each vlan entry vid numbers vid bit[12 - 2] in vla n tag vid bit[1 - 0] in vlan tag 0 bits[12 - 0] 0 0 0 0 bits[25 - 13] 1 0 1 0 bits[38 - 26] 2 0 2 0 bits[51 - 39] 3 0 3 1 bits[12 - 0] 4 1 0 1 bits[25 - 13] 5 1 1 1 bits[38 - 26] 6 1 2 1 bits[51 - 39] 7 1 3 2 bits[12 - 0] 8 2 0 2 bits[25 - 13] 9 2 1 2 bits[38 - 26] 10 2 2 2 bits[51 - 39] 11 2 3 : : : : : : : : : : : : : : : 1023 bits[12 - 0] 4092 1023 0 1023 bits[25 - 13] 4093 1023 1 1023 bits[38 - 26] 4094 1023 2 1023 bits[51 - 39] 4095 1023 3 table 17. vlan id and indirect registers micrel, inc. ksz8895mq/rq/fmq january 22, 2013 95 r evision 1. 6 dynamic mac address table this table is read only. the contents are maintained by the ksz8895mq/rq/fmq only. address name description mode default format of dynamic mac address table (1k entries) 7 1 mac empty 1, there is no valid entry in the table. 0, there a re valid entries in the table. ro 1 70? 6 1 no of valid entries indicates how many valid entries in the table. 0x3ff means 1k entries 0x1 and bit 71 = 0: means 2 entries 0x0 and bit 71 = 0: means 1 entry 0x0 and bit 71 = 1: means 0 entry ro 0 60-5 9 ti me stamp 2 - bit counters for internal aging ro 5 8 -5 6 source port the source port where fid+mac is learned. 000 p ort 1 001 po rt 2 010 p ort 3 011 p ort 4 100 p ort 5 ro 0x0 55 data ready 1, the entry is not ready, retry until this bit is set to 0. 0, th e entry is ready. ro 54? 48 fid filter id. ro 0x0 47? 0 mac address 48- bit mac address. ro 0x0 table 18. dynamic mac address table examples : (1) dynamic mac address table read (read the 1 st entry), and retrieve the mac table siz e write to register 110 with 0x18 (read dynamic table selected) write to register 111 with 0x0 (trigger the read operation) and then read register 112 (71 - 64) read register 113 (63 - 56); // the above two registers show # of entries read register 114 (55 - 48) // if bit 55 is 1, restart (reread) from this register read register 115 (47 - 40) read register 116 (39 - 32) read register 117 (31 - 24) read register 118 (23 - 16) read register 119 (15 - 8) read register 120 (7 - 0) (2) dynamic mac address table read (read the 257 th entry), without retrieving # of entries information write to register 110 with 0x19 (read dynamic table selected) write to register 111 with 0x1 (trigger the read operation) and then read register 112 (71 - 64) read register 113 (63 - 56) read reg ister 114 (55 - 48) // if bit 55 is 1, restart (reread) from this register read register 115 (47 - 40) read register 116 (39 - 32) read register 117 (31 - 24) read register 118 (23 - 16) read register 119 (15 - 8) read register 120 (7 - 0) micrel, inc. ksz8895mq/rq/fmq january 22, 2013 96 r evision 1. 6 mib (management informa tion base) counters the mib counters are provided on per port basis. th es e counters are read using indirect memory access as below: for port 1 offset counter name description 0x0 rxloprioritybyte rx lo - priority (default) octet count including bad pac kets. 0x1 rxhiprioritybyte rx hi - priority octet count including bad packets. 0x2 rxundersizepkt rx undersize packets w/good crc. 0x3 rxfragments rx fragment packets w/bad crc, symbol errors or alignment errors. 0x4 rxoversize rx oversize pa ckets w/good crc (max: 1536 or 1522 bytes). 0x5 rxjabbers rx packets longer than 1522b w/either crc errors, alignment errors, or symbol errors (depends on max packet size setting) or rx packets longer than 1916b only. 0x6 rxsymbolerror rx packets w / invalid data symbol and legal preamble, packet size. 0x7 rxcrcerror rx packets within (64,1522) bytes w/an integral number of bytes and a bad crc (upper limit depends on max packet size setting). 0x8 rxalignmenterror rx packets within (64,1522) b ytes w/a non - integral number of bytes and a bad crc (upper limit depends on max packet size setting). 0x9 rxcontrol8808pkts the number of mac control frames received by a port with 88 - 08h in ethertype field. 0xa rxpausepkts the number of pause fram es received by a port. pause frame is qualified with ethertype (88 - 08h), da, control opcode (00 - 01), data length (64b min), and a valid crc. 0xb rxbroadcast rx good broadcast packets ( not including errored broadcast packets or valid multicast packets). 0xc rxmulticast rx good multicast packets ( not including mac control frames, errored multicast packets or valid broadcast packets). 0xd rxunicast rx good unicast packets. 0xe rx64octets total rx packets (bad packets included) that were 64 octe ts in length. 0xf rx65to127octets total rx packets (bad packets included) that are between 65 and 127 octets in length. 0x10 rx128to255octets total rx packets (bad packets included) that are between 128 and 255 octets in length. 0x11 rx256to511o ctets total rx packets (bad packets included) that are between 256 and 511 octets in length. 0x12 rx512to1023octets total rx packets (bad packets included) that are between 512 and 1023 octets in length. 0x13 rx1024to1522octets total rx packets (b ad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting). 0x14 txloprioritybyte tx lo - priority good octet count, including pause packets. 0x15 txhiprioritybyte tx hi - priority good octet c ount, including pause packets. 0x16 txlatecollision the number of times a collision is detected later than 512 bit - times into the tx of a packet. 0x17 txpausepkts the number of pause frames transmitted by a port. 0x18 txbroadcastpkts tx good br oadcast packets ( not including errored broadcast or valid multicast packets). 0x19 txmulticastpkts tx good multicast packets ( not including errored multicast packets or valid broadcast packets). 0x1a txunicastpkts tx good unicast packets. 0x1b t xdeferred tx packets by a port for which the 1 st tx attempt is delayed due to the busy medium. 0x1c txtotalcollision tx total collision, half - duplex only. 0x1d txexcessivecollision a count of frames for which tx fails due to excessive collisions. 0x1e txsinglecollision successfully tx frames on a port for which tx is inhibited by exactly one collision. 0x1f txmultiplecollision successfully tx frames on a port for which tx is inhibited by more than one collision. table 19. port1 mib counter indirect memory offerts micrel, inc. ksz8895mq/rq/fmq january 22, 2013 97 r evision 1. 6 for port 2, the base is 0x20, same offset definition (0x20 - 0x3f) for port 3, the base is 0x40, same offset definition (0x40 - 0x5f) for port 4, the base is 0x60, same offset definition (0x60 - 0x7f) for port 5, the base is 0x80, same offset definition (0x80 - 0x9f) address name description mode default format of per port mib counters (16 entries) 31 overflow 1, counter overflow. 0, no counter overflow. ro 0 30 count valid 1, counter value is valid. 0 , counter value is not valid. ro 0 29? 0 counter values counter value. ro 0 table 20. format of ? per port ? mib counter offset counter name description 0x100 port1 tx drop packets tx packets dropped due to lack of resour ces. 0x101 port2 tx drop packets tx packets dropped due to lack of resources. 0x102 port3 tx drop packets tx packets dropped due to lack of resources. 0x103 port4 tx drop packets tx packets dropped due to lack of resources. 0x104 port5 tx dr op packets tx packets dropped due to lack of resources. 0x105 port1 rx drop packets rx packets dropped due to lack of resources. 0x106 port2 rx drop packets rx packets dropped due to lack of resources. 0x107 port3 rx drop packets rx packets dr opped due to lack of resources. 0x108 port4 rx drop packets rx packets dropped due to lack of resources. 0x109 port5 rx drop packets rx packets dropped due to lack of resources. table 21. all port dropped packet mib count ers address name description mode default format of all port dropped packet mib counters 30? 16 reserved reserved. n/a n/a 15? 0 counter values counter value. ro 0 table 22. format of ? all dropped packet ? mib counter no t e: all port dropped packet mib counters do not indicate overflow or validity; therefore the application must keep track of overflow and valid conditions. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 98 r evision 1. 6 the ksz8895mq/rq/fmq provides a total of 34 mib counter s per port . these counter s are used to monit or the port detail activity for network management and maintenance. these mib counters are read using in direct memory access , per the following examples. programming examples: (1) mib counter read (read port 1 r x64 octets counter) write to register 110 with 0x1c (read mib counters selected) write to register 111 with 0xe (trigger the read operation) then read register 117 (counter value 31 - 24) // if bit 31 = 1, there was a counter overflow // if bit 30 = 0, restart (reread) from this register read register 11 8 (counter value 23 - 16) read register 119 (counter value 15 - 8) read register 120 (counter value 7 - 0) (2) mib counter read (read port 2 rx64octets counter) write to register 110 with 0x1c (read mib counter selected) write to register 111 with 0x2e (trigger t he read operation) then read register 117 (counter value 31 - 24) //if bit 31 = 1, there was a counter overflow //if bit 30 = 0, restart (reread) from this register read register 118 (counter value 23 - 16) read register 119 (counter value 15 - 8) read register 120 (counter value 7 - 0) (3) mib counter read (read port 1 tx drop packets) write to register 110 with 0x1d write to register 111 with 0x00 then read register 119 (counter value 15 - 8) read register 120 (counter value 7 - 0) not e: to read out all the counters, the best performance over the spi bus is (160+3) 8 80 = 104us, where there are 160 registers, 3 overhead, 8 clocks per access, at 12.5mhz. in the heaviest condition, the byte counter will overflow in 2 minutes. it is recommended that the software read all the counters at least every 30 seconds. the per port mib counters are designed as ?read clear.? a per port mib counter will b e cleared after it is accessed. all port dropped packet mib counters are not cleared after they are accessed. the application n eeds to keep track of overflow and valid conditions on these counters. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 99 r evision 1. 6 miim registers all the registers defined in this section can be also accessed via the spi interface. not e: different mapping mechanisms are used for miim and spi. the ?phyad? defined i n ieee is assigned as ?0x1? for p ort 1, ?0x2? for port 2, ?0x3? for port 3, ?0x4? for port 4, and ?0x5? for p ort 5. the ?regad? supported are 0 x0 - 0x5 (0h - 5h), 0x1d (1dh) and 0x1f (1fh) . address name description mode default register 0h: mii control 1 5 soft reset 1, phy soft reset. 0, normal operation. r/w (sc) 0 14 loop back 1 = perform mac loopback, loop back path as follows: assume the loop - back is at p ort 1 mac , p ort 2 is the monitor port. port 1 mac loopback (p ort 1 reg. 0, bit 1 4 = ?1?) start: rxp2/rxm2 (p ort 2). can also start from port 3, 4, 5 loopback: mac/phy interface of p ort 1?s mac end: txp2/txm2 (port 2). can also end at p ort s 3, 4, 5 respectively setting address ox3,4,5 reg. 0 , bit 14 = ?1 ? will perform mac loopback on p ort s 3, 4, 5 respectively. 0 = normal operation. r/w 0 13 force 100 1, 100mbps. 0, 10mbps. r/w 1 12 an enable 1, auto - negotiation enabled. 0, auto - negotiation disabled. r/w 1 11 power down 1, power down. 0, normal operation. r/w 0 10 phy isolate 1, electrical phy isolation of phy from tx+/tx - . 0, normal operation. r/w 0 9 restart an 1, restart auto - negotiation. 0, normal operation. r/w 0 8 force full duplex 1, full duplex. 0, half duplex. r/w 0 7 collision test not supported. ro 0 6 reserved ro 0 5 hp_mdix 1 = hp auto mdi/mdi - x mode 0 = micrel auto mdi/mdi - x mode r/w 1 4 force mdi 1, force mdi. 0, normal operation. r/w 0 3 disable auto mdi/mdi - x 1, disable auto mdi/mdi - x. 0, nor mal operation. r/w 0 2 disable far end fault 1, disable far end fault detection. 0, normal operation. r/w 0 1 disable transmit 1, disable transmit. 0, normal operation. r/w 0 0 disable led 1, disable led. 0, normal operation. r/w 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 100 r evision 1. 6 miim registers (continued) address name description mode default register 1h: mii status 15 t4 capable 0, not 100 baset4 capable. ro 0 14 100 full capable 1, 100base - tx full - duplex capable. 0, not capable of 100base - tx full - duplex. ro 1 13 100 ha lf capable 1, 100base - tx half - duplex capable. 0, not 100base - tx half - duplex capable. ro 1 12 10 full capable 1, 10base - t full - duplex capable. 0, not 10base - t full - duplex capable. ro 1 11 10 half capable 1, 10base - t half - duplex capable. 0, 10bas e - t half - duplex capable. ro 1 10? 7 reserved ro 0 6 preamble suppressed not supported. ro 0 5 an complete 1, auto - negotiation complete. 0, auto - negotiation not completed. ro 0 4 far end fault 1, far end fault detected. 0, no far end fault detected. ro 0 3 an capable 1, auto - negotiation capable. 0, not auto - negotiation capable. ro 1 2 link status 1, link is up. 0, link is down. ro 0 1 jabber test not supported. ro 0 0 extended capable 0, not extended register capable. ro 0 register 2h: phyid high 15? 0 phyid high high order phyid bits. ro 0x0022 register 3h: phyid low 15? 0 phyid low low order phyid bits. ro 0x1450 register 4h: advertisement ability 15 next page not supported. ro 0 14 reserved ro 0 13 remote faul t not supported. ro 0 12? 11 reserved ro 0 10 pause 1, advertise pause ability. 0, do not advertise pause ability. r/w 1 9 reserved r/w 0 8 adv 100 full 1, advertise 100 full - duplex ability. 0, do not advertise 100 full - duplex ability. r/ w 1 7 adv 100 half 1, advertise 100 half - duplex ability. 0, do not advertise 100 half - duplex ability. r/w 1 6 adv 10 full 1, advertise 10 full - duplex ability. 0, do not advertise 10 full - duplex ability. r/w 1 5 adv 10 half 1, advertise 10 half - duplex ability. 0, do not advertise 10 half - duplex ability. r/w 1 4 ? 0 selector field 802.3 ro 00001 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 101 r evision 1. 6 miim registers (continued) address name description mode default register 5h: link partner ability 15 next page not supported. ro 0 14 l p ack not supported. ro 0 13 remote fault not supported. ro 0 12? 11 reserved ro 0 10 pause 1, link partner flow control capable. 0, link partner not flow control capable. ro 0 9 reserved ro 0 address name description mode default 8 a dv 100 full 1, link partner 100bt full - duplex capable. 0, link partner not 100bt full - duplex capable. ro 0 7 adv 100 half 1, link partner 100bt half - duplex capable. 0, link partner not 100bt half - duplex capable. ro 0 6 adv 10 full 1, link partne r 10bt full - duplex capable. 0, link partner not 10bt full - duplex capable. ro 0 5 adv 10 half 1, link partner 10bt half - duplex capable. 0, link partner not 10bt half - duplex capable. ro 0 4 -0 reserved ro 00001 register 1dh: reserved 15 reserved ro 0 14-13 reserved ro 00 12 reserved ro 0 11-9 reserved ro 0 8 ? 0 reserved ro 000000000 register 1fh: phy special control/status 15? 11 reserved ro 0000000000 10? 8 port operation mode indication indicate the current state of port operation mode: [000] = reserved [001] = still in auto - negotiation [010] = 10base - t half duplex [011] = 100base - tx half duplex [100] = reserved [101] = 10base - t full duplex [110] = 100base - tx full duplex [111] = phy/mii isolate ro 000 7 ? 6 reserved n/a, do not chan ge r/w xx 5 polrvs 1 = polarity is reversed 0 = polarity is not reversed ro 0 4 mdi - x status 1 = mdi - x 0 = mdi ro 0 3 force_lnk 1 = force link pass 0 = normal operation r/w 0 2 pwrsave 1 = enable power save 0 = disable power save r/w 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 102 r evision 1. 6 miim register s (continued) address name description mode default 1 remote loopback 1 = perform remote loopback, loop back path as follows: port 1 ( phy id address 0x1 reg. 1f , bit 1 = ?1?) start: rxp1/rxm1 (port 1) loopback: pmd/pma of port 1?s phy end: txp1/txm1 (port 1) setting phy id address 0x2,3,4,5 reg. 1f , bit 1 = ?1? will perform remote loopback on port 2, 3, 4, 5. 0 = normal operation. r/w 0 0 reserved ro 0 micrel, inc. ksz8895mq/rq/fmq january 22, 2013 103 r evision 1. 6 absolute maximum ratings (1) supply voltage ( v ddar , v ddap , v ddc ) ....................... ? 0.5v to +2.4v (v ddat , v ddio ) ................................. ? 0.5v to +4.0v input voltage ........................................ ? 0.5v to +4.0v output voltage ..................................... ? 0.5v to +4.0v lead temperature (soldering, 10 sec.) .............. 2 6 0c storage temperature (t s ) .................? 55c to +150c h bm esd rating ................................................... 4 kv operating ratings (2) suppl y voltage (v ddar , v ddap , v ddc ) ................... +1.1 4 v to +1. 26 v (v ddat ) ....................................... +3.15v to +3.45v (v ddio ) ........ 3.15 to 3.45v or 2.4 to 2.6v or 1.71 to 1.89v ambient temperature (t a ) commercial .................................... ? 0c to +70c industrial ....................................... ? 40c to +85c max junction temperature (t j ) ......................... 125c package the rmal resistance (3) thermal resistance ( ja ) ..................... 41.54c/w thermal resistance ( jc ) ..................... 19.78c/w electrical characteristics (4, 5) v in = 1.2v/3.3v (typ.); t a = 25 c symbol parameter condition min . typ . max . units 100base - tx operation ? all ports 100% utilization i dx 100b ase - tx (transmitter) 3.3v analog v ddat 129 ma i dd a 100base - tx 1.2v analog v ddar 40 ma i ddc 100base - tx 1.2v digital v ddc 45 ma i ddio 100base - tx (digital io) 3.3v digital v ddio 2.5 ma 10base - t operation ? all ports 100% utilization i dx 10base - t (transmitter) 3.3v analog v ddat 124 ma i dd a 10base -t 1.2v analog v ddar 15 ma i ddc 10base -t 1.2v digital v ddc 56 ma i ddio 10base - t (digital io) 3.3v digital v ddio 2 ma auto - negotiation mode i dx 10base - t (transmitter) 3.3v ana log v ddat 75 ma i dd a 10base -t 1.2v analog v ddar 3 9 ma i edm 10base -t 1.2v digital v ddc 58 ma i ddio 10base - t (digital io) 3.3v digital v ddio 1.6 ma power management mode i psm1 power saving mode 3.3v v ddat + v dd io 38 ma i psm2 pow er saving mode 1.2v v dd ar + vddc 73 ma i spdm1 soft power down mode 3.3v v ddat + v ddio 1.6 ma i spdm2 soft power down mode 1.2v v dd ar + vddc 0.8 ma i edm1 energy detect mode 3.3v v ddat + v ddio 7.5 ma i edm2 energy detect mode 1.2v v dd ar + vddc 46 ma notes: 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to function outside its operating rating. unused inputs must always be tied to an appropriate lo gic voltage level (ground or v dd ). 3. no heat sp reader in package. the thermal junction to ambient ( ja ) and the thermal junction to case ( jc ) are under air velocity 0m/s. 4. specification for packaged product only. there is no an additional transformer consumption due to use on chip termination tec hnology with internal biasing for 10bese - t and 100base - tx . 5. measurements were taken with operating ratings. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 104 r evision 1. 6 electrical characteristics (4, 5) (continued) v in = 1.2v/3.3v (typ.); t a = 25 c symbol parameter condition min. typ. max. units ttl inputs v ih input high voltage ( vddio=3.3/2.5/1.8v) 2.0/ 1 . 8 /1.3 v v il input low voltage ( vddio=3.3/2.5/1.8v) 0.8/0. 7 /0. 5 v i in input current (excluding pull - up/pull - down) v in = gnd ~ v ddio ? 10 10 a ttl outputs v oh output high voltage ( vddio=3.3/2.5/1.8v) i oh = ? 8ma 2.4/ 2 . 0 /1.5 v v ol output low voltage ( vddio=3.3/2.5/1.8v) i ol = 8ma 0.4/0.4 /0. 3 v i oz output tri - state leakage v in = gnd ~ v ddio 10 a 100base - tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100? termination on the differenti al output 0.95 1.05 v v imb output voltage imbalance 100? termination on the differential output 2 % t r t t rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.5 ns overshoot 5 % output jitters peak - to - p eak 0 0.75 1.4 ns 10base - t receive v sq squelch threshold 5mhz square wave 300 400 585 mv 10base - t transmit (measured differentially after 1:1 transformer) v ddat = 3 . 3 v v p peak differential output voltage 100? termination on the differential output 2.2 2. 5 2.8 v output jitters peak - to - peak 1.4 3.5 ns rise/fall times 28 30 ns micrel, inc. ksz8895mq/rq/fmq january 22, 2013 105 r evision 1. 6 timing diagrams eeprom timing figure 13 . eeprom interface input receive timing diagram figure 14. eeprom interface output transmit timing diagram symbol parameter min . typ . max . units t cyc1 clock cycle 16384 ns t s1 set - up time 20 ns t h1 hold time 20 ns t ov1 output valid 4096 4112 4128 ns table 23. eepr om timing parameters micrel, inc. ksz8895mq/rq/fmq january 22, 2013 106 r evision 1. 6 sni timing figure 15 . sni input timing figure 16 . sni output timing symbol parameter min . typ . max . units t cyc2 clock cycle 100 ns t s2 set - up time 10 ns t h2 hold time 0 ns t o2 output valid 0 3 6 ns table 24. sni timing parameters micrel, inc. ksz8895mq/rq/fmq january 22, 2013 107 r evision 1. 6 mii timing figure 17 . mac mode mii timing ? data received from mii figure 18 . mac mode mii timing ? data transmitted from mii 10base - t/100base - tx symbol parameter min . typ . max . units t cyc3 clock cycle 400/40 ns t s3 set - up time 10 ns t h3 hold time 5 ns t ov3 output valid 3 9 25 ns table 25. mac mode mii t iming parameters micrel, inc. ksz8895mq/rq/fmq january 22, 2013 108 r evision 1. 6 mii timing (continued) figure 19 . phy mode mii timing ? data received from mii figure 20 . phy mode mii timing ? data transmitted from mii 10baset/100baset symbol parameter min . typ . max . units t cyc4 clock cycle 400/40 ns t s4 set - up time 10 ns t h4 hold time 0 ns t ov4 output valid 1 0 2 0 2 5 ns table 26. phy mode mii timing parameters micrel, inc. ksz8895mq/rq/fmq january 22, 2013 109 r evision 1. 6 rmii timing figure 21 . rmii timing ? data receiv ed from rmii figure 22 . rmii timing ? data transmitted to rmii timing parameter description min . typ . max . unit t cyc clock cycle 20 ns t 1 setup time 4 ns t 2 hold time 2 ns t od output delay 3 1 4 ns table 27. rmii timing parameters micrel, inc. ksz8895mq/rq/fmq january 22, 2013 110 r evision 1. 6 spi timing figure 23 . spi input timing symbol parameter min . typ . max . units f c clock frequency 25 mhz t chsl spis_n inactive hold time 10 ns t slch spis_n active set - up time 10 ns t chsh spis_n active hold time 10 ns t shch spis_n inactive set - up time 10 ns t shsl spis_n deselect time 200 ns t dvch data input set - up time 5 ns t chdx data input hold time 5 ns t clch clock rise time 1 s t chcl clock fall time 1 s t dldh data input rise time 1 s t dhdl data input fall time 1 s table 28. spi input timing parameters micrel, inc. ksz8895mq/rq/fmq january 22, 2013 111 r evision 1. 6 spi timing (continued) figure 24 . spi output timing symbol parameter min . typ . max . units f c clock frequency 25 mhz t clqx spiq hold time 0 0 ns t clqv clock low to spiq valid 15 ns t ch clock high time 18 ns t cl clock low time 18 ns t qlqh spiq rise time 50 ns t qhql spiq fall time 50 ns t shqz spiq disable time 15 ns table 29. spi output timing parameters micrel, inc. ksz8895mq/rq/fmq january 22, 2013 112 r evision 1. 6 auto - negotiation timing figure 25 : auto - negotiation timing symbols parameters min . typ . max . units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulse per burst 17 33 table 30. auto - negotiation timing parameters micrel, inc. ksz8895mq/rq/fmq january 22, 2013 113 r evision 1. 6 mdc/mdio timing figure 26 . mdc/mdio timing timing parameter description min . typ . max unit t p mdc period 400 ns t 1 md1 mdio (phy input) setup to rising edge of mdc 10 ns t md2 mdio (phy input) hold from rising edge of mdc 4 ns t md3 mdio (phy output) delay from rising edge of mdc 222 ns table 31. mdc/mdio typical timing parameters micrel, inc. ksz8895mq/rq/fmq january 22, 2013 114 r evision 1. 6 reset timing figure 27 . reset timing symbol parameter mi n . typ . max . units t sr stable supply voltages to reset high 10 ms t cs configuration set - up time 50 ns t ch configuration hold time 50 ns t rc reset to strap - in pin output 50 ns tvr 3.3v rise time 100 us table 32. reset timing parameters micrel, inc. ksz8895mq/rq/fmq january 22, 2013 115 r evision 1. 6 reset circuit diagram micrel recommends the following discrete reset circuit as shown in figure 22 when powering up the ks8895mq device. for the application where the reset circuit signal comes from a not her device (e.g., cpu , fpga, etc), we recommend the reset circuit as shown in figure 23. figure 28 . recommended reset circuit figure 29 . recommended circuit for interfacing with cpu/fpga reset at power - on- reset, r, c, and d1 provide the necessary ramp rise time to reset the micrel device. the reset out rst_out_n from cpu/fpga provides the warm reset after power up. micrel, inc. ksz8895mq/rq/fmq january 22, 2013 116 r evision 1. 6 selection of isolation transformer (1) one simple 1:1 isolation transformer is needed at the line interfa ce. an isolation transformer with integrated common - mode choke is recommended for exceeding fcc requirements at line side . request to separate the center taps of rx/tx at chip side. the following table gives recommended transformer characteristics. charac teristics name value test condition turns ratio 1 ct : 1 ct open - circuit inductance (min.) 350h 100mv, 100khz, 8ma leakage inductance (max.) 0.4h 1mhz (min.) inter - winding capacitance (max.) 12pf d.c. resistance (max.) 0.9? insertion loss (max.) 1.0db 0mhz to 65mhz hipot (min.) 1500vrms table 33. transformer selection criteria not e s : 1. the ieee 802.3u standard for 100base - tx assumes a transformer loss of 0.5db. for the transmit line transform er, insertion loss of up to 1.3db can be compensated by increasing the line drive current by means of reducing the iset resistor value. 2. the center taps of rx and tx should be isolated for the low power consumption. the following transformer vendors provi de compatible magnetic parts for micrel?s device: vendor s and part s auto mdix number of ports vendor s and part s auto mdix number of ports pulse h1 6 64nl yes 4 pulse h1102 yes 1 ycl ph406 082 yes 4 bel fuse s558 - 5999- u7 yes 1 tdk tla - 6t718a yes 1 ycl pt163020 yes 1 lankom lf - h41s yes 1 transpower hb726 yes 1 datatronic nt79075 yes 1 delta lf8505 yes 1 table 34. qualified magnetic vendors selection of reference crystal chacteristics value units fr equency 25.00000 mhz frequency tolerance (max) <= 50 ppm load capacitance (max) 27 pf series resistance (max esr) 40 ? table 35. typical reference crystal characteristics micrel, inc. ksz8895mq/rq/fmq january 22, 2013 117 r evision 1. 6 package information 128- pin pqfp micrel, inc. ksz8895mq/rq/fmq january 22, 2013 118 r evision 1. 6 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.com micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in th is data sheet. this information is not intended as a warranty and m icrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptions at any time without not ice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual prope rty rights is granted by this document. except as provided in micrel?s terms and conditions of sale for such products, micrel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel p roducts including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right . micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) supp ort or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or systems is a purchaser?s own risk a nd pu rchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2011 micrel, incorporated. |
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